
Mark W. Regn
Examiner (ID: 489, Phone: (571)270-5968 , Office: P/2697 )
| Most Active Art Unit | 2697 |
| Art Unit(s) | 2629, 2694, 2697, 2622 |
| Total Applications | 468 |
| Issued Applications | 311 |
| Pending Applications | 0 |
| Abandoned Applications | 159 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10377922
[patent_doc_number] => 20150262929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'AIR-GAP SCHEME FOR BEOL PROCESS'
[patent_app_type] => utility
[patent_app_number] => 14/205878
[patent_app_country] => US
[patent_app_date] => 2014-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4779
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205878
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/205878 | Air-gap scheme for BEOL process | Mar 11, 2014 | Issued |
Array
(
[id] => 10377859
[patent_doc_number] => 20150262866
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/205093
[patent_app_country] => US
[patent_app_date] => 2014-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5680
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205093
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/205093 | Integrated circuit package | Mar 10, 2014 | Issued |
Array
(
[id] => 10184869
[patent_doc_number] => 09214553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-15
[patent_title] => 'Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device'
[patent_app_type] => utility
[patent_app_number] => 14/200952
[patent_app_country] => US
[patent_app_date] => 2014-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 7405
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 301
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200952
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/200952 | Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device | Mar 6, 2014 | Issued |
Array
(
[id] => 11564849
[patent_doc_number] => 09627443
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-18
[patent_title] => 'Three-dimensional oblique two-terminal memory with enhanced electric field'
[patent_app_type] => utility
[patent_app_number] => 14/194499
[patent_app_country] => US
[patent_app_date] => 2014-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 17929
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194499
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/194499 | Three-dimensional oblique two-terminal memory with enhanced electric field | Feb 27, 2014 | Issued |
Array
(
[id] => 9488364
[patent_doc_number] => 20140138769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-22
[patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/166432
[patent_app_country] => US
[patent_app_date] => 2014-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 75
[patent_figures_cnt] => 75
[patent_no_of_words] => 21924
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166432
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/166432 | Semiconductor device and fabrication method | Jan 27, 2014 | Issued |
Array
(
[id] => 10321888
[patent_doc_number] => 20150206892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-23
[patent_title] => 'FAST PROGRAMMING ANTIFUSE AND METHOD OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 14/159617
[patent_app_country] => US
[patent_app_date] => 2014-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5187
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159617
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/159617 | Fast programming antifuse and method of manufacture | Jan 20, 2014 | Issued |
Array
(
[id] => 15467135
[patent_doc_number] => 10549426
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Method for estimating movement of a poly-articulated mass object
[patent_app_type] => utility
[patent_app_number] => 14/758920
[patent_app_country] => US
[patent_app_date] => 2013-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5640
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14758920
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/758920 | Method for estimating movement of a poly-articulated mass object | Dec 9, 2013 | Issued |
Array
(
[id] => 9380937
[patent_doc_number] => 20140084418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-27
[patent_title] => 'LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 14/090033
[patent_app_country] => US
[patent_app_date] => 2013-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4636
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090033
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/090033 | Lateral epitaxial grown SOI in deep trench structures and methods of manufacture | Nov 25, 2013 | Issued |
Array
(
[id] => 11417603
[patent_doc_number] => 09564436
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-07
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/082529
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2182
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082529
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/082529 | Semiconductor device | Nov 17, 2013 | Issued |
Array
(
[id] => 10252228
[patent_doc_number] => 20150137224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'Semiconductor Device, Integrated Circuit and Method of Forming a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 14/082491
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11468
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082491
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/082491 | Semiconductor device, integrated circuit and method of forming a semiconductor device | Nov 17, 2013 | Issued |
Array
(
[id] => 10252327
[patent_doc_number] => 20150137323
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'METHOD FOR FABRICATING THROUGH SILICON VIA STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/080798
[patent_app_country] => US
[patent_app_date] => 2013-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3268
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080798
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/080798 | METHOD FOR FABRICATING THROUGH SILICON VIA STRUCTURE | Nov 14, 2013 | Abandoned |
Array
(
[id] => 10252275
[patent_doc_number] => 20150137271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/081019
[patent_app_country] => US
[patent_app_date] => 2013-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8019
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081019
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081019 | Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices | Nov 14, 2013 | Issued |
Array
(
[id] => 11615734
[patent_doc_number] => 09653598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-16
[patent_title] => 'Transistor component'
[patent_app_type] => utility
[patent_app_number] => 14/081375
[patent_app_country] => US
[patent_app_date] => 2013-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5261
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081375
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081375 | Transistor component | Nov 14, 2013 | Issued |
Array
(
[id] => 10793286
[patent_doc_number] => 20160139443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-19
[patent_title] => 'ARRAY SUBSTRATE, FABRICATION METHOD THEREOF, AND DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/386592
[patent_app_country] => US
[patent_app_date] => 2013-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3625
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14386592
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/386592 | Array substrate, fabrication method thereof, and display device | Nov 13, 2013 | Issued |
Array
(
[id] => 10112347
[patent_doc_number] => 09147766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-29
[patent_title] => 'Semiconductor device having fin-type channel and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 14/079681
[patent_app_country] => US
[patent_app_date] => 2013-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 4055
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079681
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/079681 | Semiconductor device having fin-type channel and method for forming the same | Nov 13, 2013 | Issued |
Array
(
[id] => 11802363
[patent_doc_number] => 09543263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-10
[patent_title] => 'Semiconductor packaging and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/077528
[patent_app_country] => US
[patent_app_date] => 2013-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 28
[patent_no_of_words] => 8266
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077528
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/077528 | Semiconductor packaging and manufacturing method thereof | Nov 11, 2013 | Issued |
Array
(
[id] => 11765264
[patent_doc_number] => 09373715
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-21
[patent_title] => 'Semiconductor devices including vertical memory cells and methods of forming same'
[patent_app_type] => utility
[patent_app_number] => 14/075480
[patent_app_country] => US
[patent_app_date] => 2013-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 9754
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075480
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/075480 | Semiconductor devices including vertical memory cells and methods of forming same | Nov 7, 2013 | Issued |
Array
(
[id] => 10244975
[patent_doc_number] => 20150129969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-14
[patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/075617
[patent_app_country] => US
[patent_app_date] => 2013-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6247
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075617
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/075617 | Semiconductor device and fabricating method thereof | Nov 7, 2013 | Issued |
Array
(
[id] => 10238183
[patent_doc_number] => 20150123177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-07
[patent_title] => 'Patterned Poly Silicon Structure as Top Electric Contact to MOS-Type Optical Modulators'
[patent_app_type] => utility
[patent_app_number] => 14/071327
[patent_app_country] => US
[patent_app_date] => 2013-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4714
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071327
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/071327 | Patterned poly silicon structure as top electric contact to MOS-type optical modulators | Nov 3, 2013 | Issued |
Array
(
[id] => 10099813
[patent_doc_number] => 09136131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-15
[patent_title] => 'Common fill of gate and source and drain contacts'
[patent_app_type] => utility
[patent_app_number] => 14/071044
[patent_app_country] => US
[patent_app_date] => 2013-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3978
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071044
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/071044 | Common fill of gate and source and drain contacts | Nov 3, 2013 | Issued |