Search

Mark W. Regn

Examiner (ID: 489, Phone: (571)270-5968 , Office: P/2697 )

Most Active Art Unit
2697
Art Unit(s)
2629, 2694, 2697, 2622
Total Applications
468
Issued Applications
311
Pending Applications
0
Abandoned Applications
159

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8506502 [patent_doc_number] => 20120305910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'HYBRID THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/234119 [patent_app_country] => US [patent_app_date] => 2011-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7113 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234119
Hybrid thin film transistor, manufacturing method thereof and display panel having the same Sep 14, 2011 Issued
Array ( [id] => 9100229 [patent_doc_number] => 08564109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Illumination apparatus' [patent_app_type] => utility [patent_app_number] => 13/233340 [patent_app_country] => US [patent_app_date] => 2011-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 9404 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13233340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/233340
Illumination apparatus Sep 14, 2011 Issued
Array ( [id] => 10004058 [patent_doc_number] => 09048156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Semiconductor image pickup device' [patent_app_type] => utility [patent_app_number] => 13/232260 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232260 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/232260
Semiconductor image pickup device Sep 13, 2011 Issued
Array ( [id] => 8037069 [patent_doc_number] => 20120068269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'Producing a perfect P-N junction' [patent_app_type] => utility [patent_app_number] => 13/232099 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9121 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20120068269.pdf [firstpage_image] =>[orig_patent_app_number] => 13232099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/232099
Producing a perfect P-N junction Sep 13, 2011 Abandoned
Array ( [id] => 7815055 [patent_doc_number] => 20120061675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'TRANSISTOR STRUCTURE, MANUFACTURING METHOD OF TRANSISTOR STRUCTURE, AND LIGHT EMITTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/232119 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 63 [patent_no_of_words] => 39794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061675.pdf [firstpage_image] =>[orig_patent_app_number] => 13232119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/232119
Transistor structure, manufacturing method of transistor structure, and light emitting apparatus Sep 13, 2011 Issued
Array ( [id] => 9965421 [patent_doc_number] => 09013037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Semiconductor package with improved pillar bump process and structure' [patent_app_type] => utility [patent_app_number] => 13/232780 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4275 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232780 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/232780
Semiconductor package with improved pillar bump process and structure Sep 13, 2011 Issued
Array ( [id] => 8705367 [patent_doc_number] => 20130062656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'THERMALLY ENHANCED OPTICAL PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/231020 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231020 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231020
THERMALLY ENHANCED OPTICAL PACKAGE Sep 12, 2011 Abandoned
Array ( [id] => 7800975 [patent_doc_number] => 08129245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Methods of manufacturing power semiconductor devices with shield and gate contacts' [patent_app_type] => utility [patent_app_number] => 13/219281 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 171 [patent_no_of_words] => 30575 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129245.pdf [firstpage_image] =>[orig_patent_app_number] => 13219281 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219281
Methods of manufacturing power semiconductor devices with shield and gate contacts Aug 25, 2011 Issued
Array ( [id] => 7564780 [patent_doc_number] => 20110284843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip' [patent_app_type] => utility [patent_app_number] => 13/198408 [patent_app_country] => US [patent_app_date] => 2011-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20110284843.pdf [firstpage_image] =>[orig_patent_app_number] => 13198408 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/198408
Probe pad on a corner stress relief region in a semiconductor chip Aug 3, 2011 Issued
Array ( [id] => 10837893 [patent_doc_number] => 08865565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'LED having a low defect N-type layer that has grown on a silicon substrate' [patent_app_type] => utility [patent_app_number] => 13/196854 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 10540 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13196854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/196854
LED having a low defect N-type layer that has grown on a silicon substrate Aug 1, 2011 Issued
Array ( [id] => 8647106 [patent_doc_number] => 20130032836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'N-TYPE GALLIUM-NITRIDE LAYER HAVING MULTIPLE CONDUCTIVE INTERVENING LAYERS' [patent_app_type] => utility [patent_app_number] => 13/196828 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13196828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/196828
N-type gallium-nitride layer having multiple conductive intervening layers Aug 1, 2011 Issued
Array ( [id] => 8647116 [patent_doc_number] => 20130032846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'NON-REACTIVE BARRIER METAL FOR EUTECTIC BONDING PROCESS' [patent_app_type] => utility [patent_app_number] => 13/196870 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10540 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13196870 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/196870
Non-reactive barrier metal for eutectic bonding process Aug 1, 2011 Issued
Array ( [id] => 10106960 [patent_doc_number] => 09142743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'High temperature gold-free wafer bonding for light emitting diodes' [patent_app_type] => utility [patent_app_number] => 13/196839 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5466 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13196839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/196839
High temperature gold-free wafer bonding for light emitting diodes Aug 1, 2011 Issued
Array ( [id] => 9245896 [patent_doc_number] => 08610179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Amorphous-silicon thin film transistor and shift register having the same' [patent_app_type] => utility [patent_app_number] => 13/193481 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9148 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193481
Amorphous-silicon thin film transistor and shift register having the same Jul 27, 2011 Issued
Array ( [id] => 7570885 [patent_doc_number] => 20110266541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip' [patent_app_type] => utility [patent_app_number] => 13/180304 [patent_app_country] => US [patent_app_date] => 2011-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266541.pdf [firstpage_image] =>[orig_patent_app_number] => 13180304 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180304
Probe pad on a corner stress relief region in a semiconductor chip Jul 10, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 9113667 [patent_doc_number] => 08569846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'MOS devices with improved source/drain regions with SiGe' [patent_app_type] => utility [patent_app_number] => 13/166481 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2796 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166481
MOS devices with improved source/drain regions with SiGe Jun 21, 2011 Issued
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