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Mark W. Tornow

Examiner (ID: 7297)

Most Active Art Unit
2891
Art Unit(s)
2891
Total Applications
1020
Issued Applications
782
Pending Applications
75
Abandoned Applications
184

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9337128 [patent_doc_number] => 20140063910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/840651 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/840651
Data verification device and a semiconductor device including the same Mar 14, 2013 Issued
Array ( [id] => 10112021 [patent_doc_number] => 09147439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof' [patent_app_type] => utility [patent_app_number] => 13/840759 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 19662 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840759 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/840759
Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof Mar 14, 2013 Issued
Array ( [id] => 9824794 [patent_doc_number] => 08934286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier' [patent_app_type] => utility [patent_app_number] => 13/747529 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5874 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13747529 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/747529
Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier Jan 22, 2013 Issued
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