Search

Martha M. Becton

Examiner (ID: 9009, Phone: (571)270-3063 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
393
Issued Applications
219
Pending Applications
1
Abandoned Applications
173

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19604418 [patent_doc_number] => 20240395298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/794825 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794825 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/794825
SEMICONDUCTOR DEVICE Aug 4, 2024 Pending
Array ( [id] => 20096117 [patent_doc_number] => 20250226053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => MEMORY DEVICE USING DATA LATCH [patent_app_type] => utility [patent_app_number] => 18/792170 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/792170
MEMORY DEVICE USING DATA LATCH Jul 31, 2024 Pending
Array ( [id] => 20182142 [patent_doc_number] => 20250266100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/792164 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/792164
MEMORY DEVICE, MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD THEREOF Jul 31, 2024 Pending
Array ( [id] => 19993751 [patent_doc_number] => 20250131973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Logging a Memory Address Associated with Faulty Usage-Based Disturbance Data [patent_app_type] => utility [patent_app_number] => 18/790365 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790365
Logging a Memory Address Associated with Faulty Usage-Based Disturbance Data Jul 30, 2024 Pending
Array ( [id] => 20422824 [patent_doc_number] => 20250384909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => MAGNETORESISTIVE MEMORY DEVICES INCLUDING DUAL FREE LAYERS AND METHODS FOR MAKING AND OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/790557 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790557 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790557
MAGNETORESISTIVE MEMORY DEVICES INCLUDING DUAL FREE LAYERS AND METHODS FOR MAKING AND OPERATING THE SAME Jul 30, 2024 Pending
Array ( [id] => 20063065 [patent_doc_number] => 20250201287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => NONVOLATILE MEMORY INTERFACE CIRCUIT, STORAGE DEVICE HAVING THE SAME AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/758015 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758015
NONVOLATILE MEMORY INTERFACE CIRCUIT, STORAGE DEVICE HAVING THE SAME AND METHOD OF OPERATING THE SAME Jun 27, 2024 Pending
Array ( [id] => 19821924 [patent_doc_number] => 20250080131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => ANALOG DIGITAL CONVERSION SENSING BY DYNAMICALLY VARYING CHARGING CAPACITOR VALUES [patent_app_type] => utility [patent_app_number] => 18/740805 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740805 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740805
ANALOG DIGITAL CONVERSION SENSING BY DYNAMICALLY VARYING CHARGING CAPACITOR VALUES Jun 11, 2024 Pending
Array ( [id] => 20153147 [patent_doc_number] => 20250252985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND OPERATING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/668263 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668263
SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM, AND OPERATING METHOD OF SEMICONDUCTOR DEVICE May 19, 2024 Pending
Array ( [id] => 20352520 [patent_doc_number] => 20250349372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => MEMORY DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/661711 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661711
Memory device and control method thereof May 12, 2024 Issued
Array ( [id] => 20338768 [patent_doc_number] => 20250342888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => CALCULATION UNIT SPLITTING FOR NAND IN-MEMORY COMPUTE [patent_app_type] => utility [patent_app_number] => 18/655122 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655122
CALCULATION UNIT SPLITTING FOR NAND IN-MEMORY COMPUTE May 2, 2024 Pending
Array ( [id] => 19531490 [patent_doc_number] => 20240355392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY PILLAR SELECTION TRANSISTOR EVALUATION [patent_app_type] => utility [patent_app_number] => 18/640902 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640902
MEMORY PILLAR SELECTION TRANSISTOR EVALUATION Apr 18, 2024 Pending
Array ( [id] => 19500140 [patent_doc_number] => 20240339158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CONTROLLING PILLAR VOLTAGE USING WORDLINE BOOST VOLTAGE AND SELECT GATE LEAKAGE DURING ALL LEVELS PROGRAMMING OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/625800 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625800
CONTROLLING PILLAR VOLTAGE USING WORDLINE BOOST VOLTAGE AND SELECT GATE LEAKAGE DURING ALL LEVELS PROGRAMMING OF A MEMORY DEVICE Apr 2, 2024 Pending
Array ( [id] => 20071892 [patent_doc_number] => 20250210114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/616177 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616177
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE Mar 25, 2024 Pending
Array ( [id] => 20036060 [patent_doc_number] => 20250174282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => OPERATION METHOD OF MEMORY, MEMORY, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/606904 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606904
OPERATION METHOD OF MEMORY, MEMORY, AND MEMORY SYSTEM Mar 14, 2024 Pending
Array ( [id] => 19435746 [patent_doc_number] => 20240304244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS [patent_app_type] => utility [patent_app_number] => 18/604192 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604192
TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS Mar 12, 2024 Pending
Array ( [id] => 19696113 [patent_doc_number] => 20250014658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/598988 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598988 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598988
STORAGE DEVICE AND OPERATING METHOD THEREOF Mar 6, 2024 Pending
Array ( [id] => 19803749 [patent_doc_number] => 20250069674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/399157 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399157
SEMICONDUCTOR DEVICE Dec 27, 2023 Pending
Array ( [id] => 20071896 [patent_doc_number] => 20250210118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => DYNAMIC BIT LINE VOLTAGE DURING PROGRAM VERIFY TO PROVIDE MORE THRESHOLD VOLTAGE BUDGET [patent_app_type] => utility [patent_app_number] => 18/390824 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390824
DYNAMIC BIT LINE VOLTAGE DURING PROGRAM VERIFY TO PROVIDE MORE THRESHOLD VOLTAGE BUDGET Dec 19, 2023 Pending
Array ( [id] => 19205882 [patent_doc_number] => 20240177781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME [patent_app_type] => utility [patent_app_number] => 18/388506 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388506
READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME Nov 8, 2023 Pending
Array ( [id] => 20002099 [patent_doc_number] => 20250140321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => WORD LINE BIAS DURING STRIPE ERASE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/384204 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384204 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384204
WORD LINE BIAS DURING STRIPE ERASE IN A MEMORY DEVICE Oct 25, 2023 Pending
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