Search

Martha M. Becton

Examiner (ID: 9009, Phone: (571)270-3063 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3749, 3743, 3762
Total Applications
393
Issued Applications
219
Pending Applications
1
Abandoned Applications
173

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19054434 [patent_doc_number] => 20240096403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/325307 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325307
Memory core circuits having cell-on-periphery structures and memory devices including the same May 29, 2023 Issued
Array ( [id] => 20332594 [patent_doc_number] => 12462878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/317362 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 7189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317362 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317362
Memory device and method of operating the same May 14, 2023 Issued
Array ( [id] => 19531485 [patent_doc_number] => 20240355387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IN-MEMORY COMPUTING METHOD [patent_app_type] => utility [patent_app_number] => 18/303726 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303726
In-memory computing (IMC) memory device and in-memory computing method Apr 19, 2023 Issued
Array ( [id] => 19191155 [patent_doc_number] => 20240170068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/300294 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300294
Memory device and operating method thereof Apr 12, 2023 Issued
Array ( [id] => 19483709 [patent_doc_number] => 20240331751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DATA STROBE LATCHING CIRCUIT AND ADJUSTING METHOD FOR ADJUSTING INTERNAL WRITE LATENCY SIGNAL [patent_app_type] => utility [patent_app_number] => 18/193648 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193648
Data strobe latching circuit and adjusting method for adjusting internal write latency signal Mar 30, 2023 Issued
Array ( [id] => 19145982 [patent_doc_number] => 20240144997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/189971 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189971
Semiconductor device Mar 23, 2023 Issued
Array ( [id] => 18743080 [patent_doc_number] => 20230352068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/124094 [patent_app_country] => US [patent_app_date] => 2023-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124094
MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF Mar 20, 2023 Issued
Array ( [id] => 19812190 [patent_doc_number] => 12243598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Semiconductor storage device and program operation method for a select gate line of the semiconductor storage device [patent_app_type] => utility [patent_app_number] => 18/176443 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 16761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176443
Semiconductor storage device and program operation method for a select gate line of the semiconductor storage device Feb 27, 2023 Issued
Array ( [id] => 20404257 [patent_doc_number] => 12494237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Clock circuitry for memory applications [patent_app_type] => utility [patent_app_number] => 18/113438 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113438 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113438
Clock circuitry for memory applications Feb 22, 2023 Issued
Array ( [id] => 19305253 [patent_doc_number] => 20240233833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => READ OFFSET COMPENSATION IN READ OPERATION OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/113616 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113616
Read offset compensation in read operation of memory device Feb 22, 2023 Issued
Array ( [id] => 19812173 [patent_doc_number] => 12243581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-03-04 [patent_title] => Output driver level-shifting latch circuit for dual-rail memory [patent_app_type] => utility [patent_app_number] => 18/110789 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110789
Output driver level-shifting latch circuit for dual-rail memory Feb 15, 2023 Issued
Array ( [id] => 19305249 [patent_doc_number] => 20240233829 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SUPER SHORT CHANNEL NOR FLASH CELL ARRAY AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/109663 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109663 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109663
Super short channel nor flash cell array and programming method thereof Feb 13, 2023 Issued
Array ( [id] => 19305249 [patent_doc_number] => 20240233829 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SUPER SHORT CHANNEL NOR FLASH CELL ARRAY AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/109663 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109663 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109663
Super short channel nor flash cell array and programming method thereof Feb 13, 2023 Issued
Array ( [id] => 19858049 [patent_doc_number] => 12260899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Decoder driver circuit and memory chip [patent_app_type] => utility [patent_app_number] => 18/155079 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7061 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155079
Decoder driver circuit and memory chip Jan 16, 2023 Issued
Array ( [id] => 18661069 [patent_doc_number] => 20230307082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => CONTROL METHOD, SEMICONDUCTOR MEMORY, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/155632 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155632
Control method, semiconductor memory, and electronic device Jan 16, 2023 Issued
Array ( [id] => 20132072 [patent_doc_number] => 12374389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Memory bank and memory [patent_app_type] => utility [patent_app_number] => 18/154292 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154292
Memory bank and memory Jan 12, 2023 Issued
Array ( [id] => 18532978 [patent_doc_number] => 20230238053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => AMPLIFICATION CIRCUIT, CONTROL METHOD, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/095364 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095364 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095364
Amplification circuit, control method, and memory Jan 9, 2023 Issued
Array ( [id] => 18514366 [patent_doc_number] => 20230230621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/149701 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149701
STORAGE DEVICE Jan 3, 2023 Pending
Array ( [id] => 20080630 [patent_doc_number] => 12354705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor device and semiconductor system [patent_app_type] => utility [patent_app_number] => 18/089322 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8318 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089322
Semiconductor device and semiconductor system Dec 26, 2022 Issued
Array ( [id] => 18379453 [patent_doc_number] => 20230154542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/984890 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/984890
NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF Nov 9, 2022 Pending
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