Martin Lerner

Array ( [id] => 19069439 [patent_doc_number] => 20240103865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => VECTOR MULTIPLY-ADD/SUBTRACT WITH INTERMEDIATE ROUNDING [patent_app_type] => utility [patent_app_number] => 18/193413 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20703130 [patent_doc_number] => 12625842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Device and method for on-the-fly processing chain reconfiguration in a streaming based neural processing unit [patent_app_type] => utility [patent_app_number] => 18/192589 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 4217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19391535 [patent_doc_number] => 20240281405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SPECIFYING A PROCESSOR WITH ASSURED AND OPPORTUNISTIC CORES [patent_app_type] => utility [patent_app_number] => 18/172943 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20257780 [patent_doc_number] => 12430130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Floating point norm instruction [patent_app_type] => utility [patent_app_number] => 18/163472 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2133 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18677799 [patent_doc_number] => 20230315446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => ARITHMETIC PROCESSING APPARATUS AND METHOD FOR ARITHMETIC PROCESSING [patent_app_type] => utility [patent_app_number] => 18/100190 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18677833 [patent_doc_number] => 20230315480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => COMPUTER-READABLE RECORDING MEDIUM STORING INSTRUCTION SEQUENCE GENERATION PROGRAM, INSTRUCTION SEQUENCE GENERATION METHOD, AND INFORMATION PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/157942 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539380 [patent_doc_number] => 20230244488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => Dual-Mode Floating Point Processor Operation [patent_app_type] => utility [patent_app_number] => 18/155834 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18378030 [patent_doc_number] => 20230153117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MEMORY-NETWORK PROCESSOR WITH PROGRAMMABLE OPTIMIZATIONS [patent_app_type] => utility [patent_app_number] => 18/092712 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18832533 [patent_doc_number] => 20230401060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => PROCESSING UNIT, COMPUTING DEVICE AND INSTRUCTION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/148654 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283786 [patent_doc_number] => 20240220262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => INSTRUCTIONS AND SUPPORT FOR CONDITIONAL COMPARISON AND TEST [patent_app_type] => utility [patent_app_number] => 18/091628 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19905771 [patent_doc_number] => 12282779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Instruction retirement unit, instruction execution unit, processing unit, computing device, and instruction processing method for performing retirement processing on instructions based on instruction completion information [patent_app_type] => utility [patent_app_number] => 18/148759 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8733 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19189852 [patent_doc_number] => 20240168765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => STORAGE OF TENSOR IN A CACHE [patent_app_type] => utility [patent_app_number] => 18/086478 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 82783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19251003 [patent_doc_number] => 20240201993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Data Evaluation Using Processing-in-Memory [patent_app_type] => utility [patent_app_number] => 18/067506 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19251009 [patent_doc_number] => 20240201999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => ACCELERATING FETCH TARGET QUEUE (FTQ) PROCESSING IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/083249 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20265776 [patent_doc_number] => 12436767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => System and method for scheduling operations in a graphics pipeline [patent_app_type] => utility [patent_app_number] => 18/066115 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19956706 [patent_doc_number] => 12327121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Instruction scheduling method, instruction scheduling apparatus, device and storage medium based on durations consumed by memory access instructions during instruction running scenarios [patent_app_type] => utility [patent_app_number] => 18/076592 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 875 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19190109 [patent_doc_number] => 20240169022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO SYNCHRONIZE MATRIX MULTIPLY-ACCUMULATE MEMORY TRANSACTIONS [patent_app_type] => utility [patent_app_number] => 18/072053 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18272151 [patent_doc_number] => 20230093393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => PROCESSOR, PROCESSING METHOD, AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 18/070781 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19899520 [patent_doc_number] => 12277444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Software-defined tensor streaming multiprocessor for large-scale machine learning [patent_app_type] => utility [patent_app_number] => 17/993564 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 9785 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18257751 [patent_doc_number] => 20230084791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => HARDWARE ARCHITECTURE TO ACCELERATE GENERATIVE ADVERSARIAL NETWORKS WITH OPTIMIZED SIMD-MIMD PROCESSING ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/058114 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058114 [rel_patent_id] =>[rel_patent_doc_number] =>)