Search

Marvin Payen

Examiner (ID: 6852, Phone: (571)270-7435 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2894, 2816
Total Applications
919
Issued Applications
787
Pending Applications
28
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17500772 [patent_doc_number] => 11289482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Field effect transistor contact with reduced contact resistance [patent_app_type] => utility [patent_app_number] => 16/717503 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717503
Field effect transistor contact with reduced contact resistance Dec 16, 2019 Issued
Array ( [id] => 15717525 [patent_doc_number] => 20200105530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SYSTEM AND METHOD FOR PRECISION FORMATION OF A LATTICE ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/702092 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702092
System and method for precision formation of a lattice on a substrate Dec 2, 2019 Issued
Array ( [id] => 15718219 [patent_doc_number] => 20200105877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => METHOD FOR FORMING TRENCH SEMICONDUCTOR DEVICE HAVING SCHOTTKY BARRIER STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/701933 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701933
METHOD FOR FORMING TRENCH SEMICONDUCTOR DEVICE HAVING SCHOTTKY BARRIER STRUCTURE Dec 2, 2019 Abandoned
Array ( [id] => 17745842 [patent_doc_number] => 11393926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Multi-gate device [patent_app_type] => utility [patent_app_number] => 16/696845 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 116 [patent_no_of_words] => 11102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696845
Multi-gate device Nov 25, 2019 Issued
Array ( [id] => 15688097 [patent_doc_number] => 20200098712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SEMICONDUCTOR DEVICE AND PACKAGE ASSEMBLY INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/687089 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687089
Semiconductor device and package assembly including the same Nov 17, 2019 Issued
Array ( [id] => 17893273 [patent_doc_number] => 11456255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Impedance controlled electrical interconnection employing meta-materials [patent_app_type] => utility [patent_app_number] => 16/685623 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685623
Impedance controlled electrical interconnection employing meta-materials Nov 14, 2019 Issued
Array ( [id] => 15625357 [patent_doc_number] => 20200083083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => Micro Device Arrangement in Donor Substrate [patent_app_type] => utility [patent_app_number] => 16/684820 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684820
Micro device arrangement in donor substrate Nov 14, 2019 Issued
Array ( [id] => 15625779 [patent_doc_number] => 20200083294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => Resistive Switching Random Access Memory with Asymmetric Source and Drain [patent_app_type] => utility [patent_app_number] => 16/680203 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680203 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680203
Resistive switching random access memory with asymmetric source and drain Nov 10, 2019 Issued
Array ( [id] => 16609460 [patent_doc_number] => 10910476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Integrated structures having gallium-containing regions [patent_app_type] => utility [patent_app_number] => 16/589985 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2816 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589985
Integrated structures having gallium-containing regions Sep 30, 2019 Issued
Array ( [id] => 19081124 [patent_doc_number] => 11950520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Optically switchable memory [patent_app_type] => utility [patent_app_number] => 17/270279 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 12727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17270279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/270279
Optically switchable memory Aug 18, 2019 Issued
Array ( [id] => 15598261 [patent_doc_number] => 20200075665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => HIGH-RESOLUTION DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/536514 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536514
High-resolution display device Aug 8, 2019 Issued
Array ( [id] => 16479570 [patent_doc_number] => 10854524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Power semiconductor module [patent_app_type] => utility [patent_app_number] => 16/531296 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531296
Power semiconductor module Aug 4, 2019 Issued
Array ( [id] => 15760711 [patent_doc_number] => 10622488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => NAND flash memory with vertical cell stack structure and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 16/521066 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 49 [patent_no_of_words] => 9251 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 528 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521066
NAND flash memory with vertical cell stack structure and method for manufacturing same Jul 23, 2019 Issued
Array ( [id] => 18344256 [patent_doc_number] => 11641748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Pretreatment method of selector device [patent_app_type] => utility [patent_app_number] => 17/042954 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2906 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17042954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/042954
Pretreatment method of selector device Jul 11, 2019 Issued
Array ( [id] => 15515579 [patent_doc_number] => 10564371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Waveguide sheet and photoelectric conversion device [patent_app_type] => utility [patent_app_number] => 16/437494 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437494 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/437494
Waveguide sheet and photoelectric conversion device Jun 10, 2019 Issued
Array ( [id] => 17093134 [patent_doc_number] => 11121332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Foldable array substrate, preparation method thereof and display device [patent_app_type] => utility [patent_app_number] => 16/410271 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410271
Foldable array substrate, preparation method thereof and display device May 12, 2019 Issued
Array ( [id] => 15475401 [patent_doc_number] => 10553586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Stacked complementary junction FETs for analog electronic circuits [patent_app_type] => utility [patent_app_number] => 16/399370 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 8666 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399370
Stacked complementary junction FETs for analog electronic circuits Apr 29, 2019 Issued
Array ( [id] => 17410287 [patent_doc_number] => 11251185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Stacked complementary junction FETs for analog electronic circuits [patent_app_type] => utility [patent_app_number] => 16/399405 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 8667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399405
Stacked complementary junction FETs for analog electronic circuits Apr 29, 2019 Issued
Array ( [id] => 14722617 [patent_doc_number] => 20190252372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/395593 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395593
Semiconductor device Apr 25, 2019 Issued
Array ( [id] => 14722635 [patent_doc_number] => 20190252381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => Field Effect Transistor Contact with Reduced Contact Resistance [patent_app_type] => utility [patent_app_number] => 16/390744 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390744 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390744
Field effect transistor contact with reduced contact resistance Apr 21, 2019 Issued
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