Search

Marvin Payen

Examiner (ID: 19064, Phone: (571)270-7435 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2894, 2816
Total Applications
945
Issued Applications
795
Pending Applications
40
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17047942 [patent_doc_number] => 11101132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method and device for bonding of substrates [patent_app_type] => utility [patent_app_number] => 16/880139 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10591 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880139
Method and device for bonding of substrates May 20, 2020 Issued
Array ( [id] => 16936944 [patent_doc_number] => 20210202833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => VARIABLE RESISTANCE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/875119 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875119
Variable resistance memory device May 14, 2020 Issued
Array ( [id] => 18032158 [patent_doc_number] => 11515358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Semiconductor devices including a passive material between memory cells and conductive access lines [patent_app_type] => utility [patent_app_number] => 16/863555 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7951 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863555
Semiconductor devices including a passive material between memory cells and conductive access lines Apr 29, 2020 Issued
Array ( [id] => 17700439 [patent_doc_number] => 11374174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Deposition mask and method of manufacturing display device using the same [patent_app_type] => utility [patent_app_number] => 16/861350 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 6723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861350
Deposition mask and method of manufacturing display device using the same Apr 28, 2020 Issued
Array ( [id] => 16487957 [patent_doc_number] => 20200381566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/816520 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816520 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/816520
NAND flash memory with vertical cell stack structure and method for manufacturing same Mar 11, 2020 Issued
Array ( [id] => 16098357 [patent_doc_number] => 20200203165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD AND DEVICE FOR BONDING OF SUBSTRATES [patent_app_type] => utility [patent_app_number] => 16/809651 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809651
Method and device for bonding of substrates Mar 4, 2020 Issued
Array ( [id] => 18137244 [patent_doc_number] => 11562933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device [patent_app_type] => utility [patent_app_number] => 16/800448 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4485 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800448 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800448
Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device Feb 24, 2020 Issued
Array ( [id] => 16210679 [patent_doc_number] => 20200243669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => Semiconductor Device, Method for Manufacturing Semiconductor Device, and Electronic Appliance Having Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/778103 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/778103
Semiconductor device, method for manufacturing semiconductor device, and electronic appliance having semiconductor device Jan 30, 2020 Issued
Array ( [id] => 15905871 [patent_doc_number] => 20200152456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SYSTEMS AND METHOD FOR INTEGRATED DEVICES ON AN ENGINEERED SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/742734 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742734 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742734
Systems and method for integrated devices on an engineered substrate Jan 13, 2020 Issued
Array ( [id] => 15873481 [patent_doc_number] => 20200144144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Fine Pitch Bva Using Reconstituted Wafer With Area Array Accessible For Testing [patent_app_type] => utility [patent_app_number] => 16/734758 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734758
Fine pitch bva using reconstituted wafer with area array accessible for testing Jan 5, 2020 Issued
Array ( [id] => 16820021 [patent_doc_number] => 11004860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Non-volatile memory device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/733539 [patent_app_country] => US [patent_app_date] => 2020-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 10393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733539
Non-volatile memory device and method for fabricating the same Jan 2, 2020 Issued
Array ( [id] => 15842489 [patent_doc_number] => 20200136527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => MEMS Actuation Systems and Methods [patent_app_type] => utility [patent_app_number] => 16/730653 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730653
MEMS actuation systems and methods Dec 29, 2019 Issued
Array ( [id] => 17310451 [patent_doc_number] => 11211578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/726486 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726486
Display device Dec 23, 2019 Issued
Array ( [id] => 15873443 [patent_doc_number] => 20200144125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => FINFET CHANNEL ON OXIDE STRUCTURES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/726518 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726518 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726518
FinFET channel on oxide structures and related methods Dec 23, 2019 Issued
Array ( [id] => 15807759 [patent_doc_number] => 20200127022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => EXPOSURE MASK AND METHOD OF MANUFACTURING A SUBSTRATE USING THE EXPOSURE MASK [patent_app_type] => utility [patent_app_number] => 16/720177 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720177
Exposure mask and method of manufacturing a substrate using the exposure mask Dec 18, 2019 Issued
Array ( [id] => 17500772 [patent_doc_number] => 11289482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Field effect transistor contact with reduced contact resistance [patent_app_type] => utility [patent_app_number] => 16/717503 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717503
Field effect transistor contact with reduced contact resistance Dec 16, 2019 Issued
Array ( [id] => 15718219 [patent_doc_number] => 20200105877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => METHOD FOR FORMING TRENCH SEMICONDUCTOR DEVICE HAVING SCHOTTKY BARRIER STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/701933 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701933
METHOD FOR FORMING TRENCH SEMICONDUCTOR DEVICE HAVING SCHOTTKY BARRIER STRUCTURE Dec 2, 2019 Abandoned
Array ( [id] => 15717525 [patent_doc_number] => 20200105530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SYSTEM AND METHOD FOR PRECISION FORMATION OF A LATTICE ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/702092 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702092
System and method for precision formation of a lattice on a substrate Dec 2, 2019 Issued
Array ( [id] => 17745842 [patent_doc_number] => 11393926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Multi-gate device [patent_app_type] => utility [patent_app_number] => 16/696845 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 116 [patent_no_of_words] => 11102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696845
Multi-gate device Nov 25, 2019 Issued
Array ( [id] => 15688097 [patent_doc_number] => 20200098712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SEMICONDUCTOR DEVICE AND PACKAGE ASSEMBLY INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/687089 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687089
Semiconductor device and package assembly including the same Nov 17, 2019 Issued
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