Marvin Payen

Array ( [id] => 19548530 [patent_doc_number] => 20240365566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => RESISTIVE RANDOM-ACCESS MEMORY ELEMENTS WITH LATERAL SIDEWALL SWITCHING [patent_app_type] => utility [patent_app_number] => 18/140677 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19639703 [patent_doc_number] => 12170320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/309564 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19507980 [patent_doc_number] => 12119411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => NAND flash memory with vertical cell stack structure and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 18/305537 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 49 [patent_no_of_words] => 9301 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19502186 [patent_doc_number] => 20240341204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => HIGH-FREQUENCY, LOW-VOLTAGE SWITCH DEVICES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 18/298132 [patent_app_country] => US [patent_app_date] => 2023-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19612160 [patent_doc_number] => 12161055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Memory array, semiconductor chip and manufacturing method of memory array [patent_app_type] => utility [patent_app_number] => 18/191885 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19470806 [patent_doc_number] => 20240324476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => STACKED RESISTIVE RANDOM-ACCESS MEMORY CROSS-POINT CELL [patent_app_type] => utility [patent_app_number] => 18/186229 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18851176 [patent_doc_number] => 20230413580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SELECTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/178389 [patent_app_country] => US [patent_app_date] => 2023-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20244240 [patent_doc_number] => 12424572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/168038 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 1043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19285899 [patent_doc_number] => 20240222376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN CHANNEL DIMENSIONS [patent_app_type] => utility [patent_app_number] => 18/091714 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20443134 [patent_doc_number] => 12513980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Stacked vertical transport field effect transistor with anchors [patent_app_type] => utility [patent_app_number] => 18/068155 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19567757 [patent_doc_number] => 12142536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device [patent_app_type] => utility [patent_app_number] => 18/082155 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4503 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19928453 [patent_doc_number] => 12302767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Buffer layer in memory cell to prevent metal redeposition [patent_app_type] => utility [patent_app_number] => 18/076726 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18251334 [patent_doc_number] => 20230078373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => VARIABLE RESISTANCE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/989085 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18320272 [patent_doc_number] => 20230118400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/977164 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18162936 [patent_doc_number] => 20230029529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => DEVICES INCLUDING A PASSIVE MATERIAL BETWEEN MEMORY CELLS AND CONDUCTIVE ACCESS LINES, AND RELATED ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/937094 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18146453 [patent_doc_number] => 20230020310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => Impedance Controlled Electrical Interconnection Employing Meta-Materials [patent_app_type] => utility [patent_app_number] => 17/952838 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19000959 [patent_doc_number] => 11917837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Method of forming the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/897221 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6474 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20307081 [patent_doc_number] => 12453092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor device and fabrication method therefor [patent_app_type] => utility [patent_app_number] => 17/874861 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19110235 [patent_doc_number] => 11963369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Memory array with asymmetric bit-line architecture [patent_app_type] => utility [patent_app_number] => 17/874448 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 11474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19183782 [patent_doc_number] => 11990382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Fine pitch BVA using reconstituted wafer with area array accessible for testing [patent_app_type] => utility [patent_app_number] => 17/865994 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 8664 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865994 [rel_patent_id] =>[rel_patent_doc_number] =>)