Search

Marwan Ayash

Examiner (ID: 16675, Phone: (571)270-1179 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2133, 2185
Total Applications
416
Issued Applications
275
Pending Applications
29
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15273871 [patent_doc_number] => 20190385670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => Method and Apparatus for Optimizing Calibrations of a Memory Subsystem [patent_app_type] => utility [patent_app_number] => 16/012427 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012427 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/012427
Method and apparatus for optimizing calibrations of a memory subsystem Jun 18, 2018 Issued
Array ( [id] => 15854903 [patent_doc_number] => 10642737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Logging cache influxes by request to a higher-level cache [patent_app_type] => utility [patent_app_number] => 15/947699 [patent_app_country] => US [patent_app_date] => 2018-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 18714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/947699
Logging cache influxes by request to a higher-level cache Apr 5, 2018 Issued
Array ( [id] => 15425811 [patent_doc_number] => 10545834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => Server-assisted network data archiving [patent_app_type] => utility [patent_app_number] => 15/910746 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 13717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910746 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910746
Server-assisted network data archiving Mar 1, 2018 Issued
Array ( [id] => 12892024 [patent_doc_number] => 20180189183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => DATA STORAGE DEVICE ADJUSTING COMMAND RATE PROFILE BASED ON OPERATING MODE [patent_app_type] => utility [patent_app_number] => 15/906938 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906938
DATA STORAGE DEVICE ADJUSTING COMMAND RATE PROFILE BASED ON OPERATING MODE Feb 26, 2018 Abandoned
Array ( [id] => 14750765 [patent_doc_number] => 20190258556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => TRACE RECORDING BY LOGGING INFLUXES TO AN UPPER-LAYER SHARED CACHE, PLUS CACHE COHERENCE PROTOCOL TRANSITIONS AMONG LOWER-LAYER CACHES [patent_app_type] => utility [patent_app_number] => 15/898372 [patent_app_country] => US [patent_app_date] => 2018-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898372
Trace recording by logging influxes to an upper-layer shared cache, plus cache coherence protocol transitions among lower-layer caches Feb 15, 2018 Issued
Array ( [id] => 18519733 [patent_doc_number] => 11709624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => System-on-chip having multiple circuits and memory controller in separate and independent power domains [patent_app_type] => utility [patent_app_number] => 15/898183 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4688 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898183
System-on-chip having multiple circuits and memory controller in separate and independent power domains Feb 14, 2018 Issued
Array ( [id] => 16370998 [patent_doc_number] => 10802753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Distributed compute array in a storage system [patent_app_type] => utility [patent_app_number] => 15/898062 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898062 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898062
Distributed compute array in a storage system Feb 14, 2018 Issued
Array ( [id] => 17223530 [patent_doc_number] => 11176031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Automatic memory management using a memory management unit [patent_app_type] => utility [patent_app_number] => 15/855146 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855146 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855146
Automatic memory management using a memory management unit Dec 26, 2017 Issued
Array ( [id] => 12688555 [patent_doc_number] => 20180121351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => STORAGE SYSTEM, STORAGE MANAGEMENT APPARATUS, STORAGE DEVICE, HYBRID STORAGE APPARATUS, AND STORAGE MANAGEMENT METHOD [patent_app_type] => utility [patent_app_number] => 15/853874 [patent_app_country] => US [patent_app_date] => 2017-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/853874
STORAGE SYSTEM, STORAGE MANAGEMENT APPARATUS, STORAGE DEVICE, HYBRID STORAGE APPARATUS, AND STORAGE MANAGEMENT METHOD Dec 24, 2017 Abandoned
Array ( [id] => 16879969 [patent_doc_number] => 11030118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Data-locking memory module [patent_app_type] => utility [patent_app_number] => 15/849507 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849507
Data-locking memory module Dec 19, 2017 Issued
Array ( [id] => 16171479 [patent_doc_number] => 10713046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => System memory controller with atomic operations [patent_app_type] => utility [patent_app_number] => 15/849537 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2730 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849537 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849537
System memory controller with atomic operations Dec 19, 2017 Issued
Array ( [id] => 13905851 [patent_doc_number] => 20190042130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => PREFIX OPCODE METHOD FOR SLC ENTRY WITH AUTO-EXIT OPTION [patent_app_type] => utility [patent_app_number] => 15/845596 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845596
PREFIX OPCODE METHOD FOR SLC ENTRY WITH AUTO-EXIT OPTION Dec 17, 2017 Abandoned
Array ( [id] => 12668230 [patent_doc_number] => 20180114576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/839976 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839976 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839976
Responder signal circuitry for memory arrays finding at least one cell with a predefined value Dec 12, 2017 Issued
Array ( [id] => 17106329 [patent_doc_number] => 11126546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Garbage data scrubbing method, and device [patent_app_type] => utility [patent_app_number] => 16/754537 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 19417 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16754537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/754537
Garbage data scrubbing method, and device Oct 12, 2017 Issued
Array ( [id] => 16551781 [patent_doc_number] => 10884941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Techniques to store data for critical chunk operations [patent_app_type] => utility [patent_app_number] => 15/720027 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9072 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720027
Techniques to store data for critical chunk operations Sep 28, 2017 Issued
Array ( [id] => 16200746 [patent_doc_number] => 10725909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Memory device controlling including reading from a first memory and writing to a second memory based on timing and control signals [patent_app_type] => utility [patent_app_number] => 15/687910 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687910
Memory device controlling including reading from a first memory and writing to a second memory based on timing and control signals Aug 27, 2017 Issued
Array ( [id] => 15231839 [patent_doc_number] => 10503642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Cache coherence directory architecture with decoupled tag array and data array [patent_app_type] => utility [patent_app_number] => 15/686846 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3745 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686846
Cache coherence directory architecture with decoupled tag array and data array Aug 24, 2017 Issued
Array ( [id] => 13875545 [patent_doc_number] => 20190034113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => SYSTEMS AND METHODS FOR PROVIDING CUSTOMER SERVICE FUNCTIONALITY DURING PORTFOLIO MIGRATION DOWNTIME [patent_app_type] => utility [patent_app_number] => 15/665047 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665047
Systems and methods for providing customer service functionality during portfolio migration downtime Jul 30, 2017 Issued
Array ( [id] => 11938607 [patent_doc_number] => 20170242757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SYSTEMS AND METHODS FOR RESTORING DATA FROM NETWORK ATTACHED STORAGE' [patent_app_type] => utility [patent_app_number] => 15/589662 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8020 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589662
SYSTEMS AND METHODS FOR RESTORING DATA FROM NETWORK ATTACHED STORAGE May 7, 2017 Abandoned
Array ( [id] => 16607816 [patent_doc_number] => 10908818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Accessing deduplicated data from write-evict units in solid-state memory cache [patent_app_type] => utility [patent_app_number] => 15/488977 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 13222 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488977
Accessing deduplicated data from write-evict units in solid-state memory cache Apr 16, 2017 Issued
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