
Mary A. Wilczewski
Examiner (ID: 7484, Phone: (571)272-1849 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 1107, 2812, 2898, 2822, 1104 |
| Total Applications | 2109 |
| Issued Applications | 1700 |
| Pending Applications | 87 |
| Abandoned Applications | 341 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11869645
[patent_doc_number] => 20170236930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-17
[patent_title] => 'VERTICAL DOUBLE-DIFFUSED METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR'
[patent_app_type] => utility
[patent_app_number] => 15/323108
[patent_app_country] => US
[patent_app_date] => 2014-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5526
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15323108
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/323108 | VERTICAL DOUBLE-DIFFUSED METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR | Dec 30, 2014 | Abandoned |
Array
(
[id] => 10223656
[patent_doc_number] => 20150108649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'METHOD OF FORMING HYBRID DIFFUSION BARRIER LAYER AND SEMICONDUCTOR DEVICE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/587019
[patent_app_country] => US
[patent_app_date] => 2014-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3869
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14587019
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/587019 | Method of forming hybrid diffusion barrier layer and semiconductor device thereof | Dec 30, 2014 | Issued |
Array
(
[id] => 10402803
[patent_doc_number] => 20150287811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'Methods to integrate SONOS into CMOS Flow'
[patent_app_type] => utility
[patent_app_number] => 14/576657
[patent_app_country] => US
[patent_app_date] => 2014-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9827
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576657
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/576657 | Methods to integrate SONOS into CMOS flow | Dec 18, 2014 | Issued |
Array
(
[id] => 10402803
[patent_doc_number] => 20150287811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'Methods to integrate SONOS into CMOS Flow'
[patent_app_type] => utility
[patent_app_number] => 14/576657
[patent_app_country] => US
[patent_app_date] => 2014-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9827
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576657
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/576657 | Methods to integrate SONOS into CMOS flow | Dec 18, 2014 | Issued |
Array
(
[id] => 10402803
[patent_doc_number] => 20150287811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'Methods to integrate SONOS into CMOS Flow'
[patent_app_type] => utility
[patent_app_number] => 14/576657
[patent_app_country] => US
[patent_app_date] => 2014-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9827
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576657
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/576657 | Methods to integrate SONOS into CMOS flow | Dec 18, 2014 | Issued |
Array
(
[id] => 10402803
[patent_doc_number] => 20150287811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'Methods to integrate SONOS into CMOS Flow'
[patent_app_type] => utility
[patent_app_number] => 14/576657
[patent_app_country] => US
[patent_app_date] => 2014-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9827
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576657
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/576657 | Methods to integrate SONOS into CMOS flow | Dec 18, 2014 | Issued |
Array
(
[id] => 10217429
[patent_doc_number] => 20150102422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/551606
[patent_app_country] => US
[patent_app_date] => 2014-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4101
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14551606
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/551606 | Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same | Nov 23, 2014 | Issued |
Array
(
[id] => 10792026
[patent_doc_number] => 20160138182
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-19
[patent_title] => 'METHODS FOR FORMING MIXED METAL OXIDE EPITAXIAL FILMS'
[patent_app_type] => utility
[patent_app_number] => 14/546199
[patent_app_country] => US
[patent_app_date] => 2014-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3824
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546199
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/546199 | METHODS FOR FORMING MIXED METAL OXIDE EPITAXIAL FILMS | Nov 17, 2014 | Abandoned |
Array
(
[id] => 9909701
[patent_doc_number] => 20150064902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-05
[patent_title] => 'Methods of Fabricating Semiconductor Devices'
[patent_app_type] => utility
[patent_app_number] => 14/535609
[patent_app_country] => US
[patent_app_date] => 2014-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 14012
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14535609
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/535609 | Methods of fabricating semiconductor devices | Nov 6, 2014 | Issued |
Array
(
[id] => 14769105
[patent_doc_number] => 10395954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Method and device for coating a product substrate
[patent_app_type] => utility
[patent_app_number] => 15/520201
[patent_app_country] => US
[patent_app_date] => 2014-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 6193
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520201
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/520201 | Method and device for coating a product substrate | Nov 4, 2014 | Issued |
Array
(
[id] => 16831266
[patent_doc_number] => 11007497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-18
[patent_title] => Gas jetting apparatus
[patent_app_type] => utility
[patent_app_number] => 15/516598
[patent_app_country] => US
[patent_app_date] => 2014-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 13746
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516598
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/516598 | Gas jetting apparatus | Oct 28, 2014 | Issued |
Array
(
[id] => 11773782
[patent_doc_number] => 09382627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-05
[patent_title] => 'Methods and materials for anchoring gapfill metals'
[patent_app_type] => utility
[patent_app_number] => 14/515816
[patent_app_country] => US
[patent_app_date] => 2014-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6507
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515816
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/515816 | Methods and materials for anchoring gapfill metals | Oct 15, 2014 | Issued |
Array
(
[id] => 11753505
[patent_doc_number] => 09711522
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-18
[patent_title] => 'Memory hole structure in three dimensional memory'
[patent_app_type] => utility
[patent_app_number] => 14/506477
[patent_app_country] => US
[patent_app_date] => 2014-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 49
[patent_no_of_words] => 8495
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14506477
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/506477 | Memory hole structure in three dimensional memory | Oct 2, 2014 | Issued |
Array
(
[id] => 10321951
[patent_doc_number] => 20150206955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-23
[patent_title] => 'METHODS OF SELECTIVELY GROWING SOURCE/DRAIN REGIONS OF FIN FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING A FIN FIELD EFFECT TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 14/498996
[patent_app_country] => US
[patent_app_date] => 2014-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 7760
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498996
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/498996 | Methods of selectively growing source/drain regions of fin field effect transistor and method of manufacturing semiconductor device including a fin field effect transistor | Sep 25, 2014 | Issued |
Array
(
[id] => 10196061
[patent_doc_number] => 09224977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-29
[patent_title] => 'Method of manufacturing organic electroluminescent display device'
[patent_app_type] => utility
[patent_app_number] => 14/497378
[patent_app_country] => US
[patent_app_date] => 2014-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3414
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497378
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/497378 | Method of manufacturing organic electroluminescent display device | Sep 25, 2014 | Issued |
Array
(
[id] => 10022213
[patent_doc_number] => 09064706
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Composite of III-nitride crystal on laterally stacked substrates'
[patent_app_type] => utility
[patent_app_number] => 14/491962
[patent_app_country] => US
[patent_app_date] => 2014-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 45
[patent_no_of_words] => 19127
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491962
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/491962 | Composite of III-nitride crystal on laterally stacked substrates | Sep 18, 2014 | Issued |
Array
(
[id] => 10645263
[patent_doc_number] => 09362136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-07
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/477115
[patent_app_country] => US
[patent_app_date] => 2014-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 53
[patent_no_of_words] => 24803
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477115
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/477115 | Method of manufacturing semiconductor device | Sep 3, 2014 | Issued |
Array
(
[id] => 11898405
[patent_doc_number] => 09768351
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'Optoelectronic semiconductor device with barrier layer'
[patent_app_type] => utility
[patent_app_number] => 14/475210
[patent_app_country] => US
[patent_app_date] => 2014-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2531
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475210
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/475210 | Optoelectronic semiconductor device with barrier layer | Sep 1, 2014 | Issued |
Array
(
[id] => 10252367
[patent_doc_number] => 20150137364
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/470831
[patent_app_country] => US
[patent_app_date] => 2014-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5478
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14470831
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/470831 | Stacked microelectronic devices | Aug 26, 2014 | Issued |
Array
(
[id] => 10597239
[patent_doc_number] => 09318334
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-19
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/469606
[patent_app_country] => US
[patent_app_date] => 2014-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2090
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14469606
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/469606 | Method for fabricating semiconductor device | Aug 26, 2014 | Issued |