Search

Mary A. Wilczewski

Examiner (ID: 17247, Phone: (571)272-1849 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2898, 1107, 1104, 2812
Total Applications
2125
Issued Applications
1716
Pending Applications
77
Abandoned Applications
344

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18194336 [patent_doc_number] => 20230047855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => LIGHT IRRADIATION TYPE HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS [patent_app_type] => utility [patent_app_number] => 17/975720 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975720
LIGHT IRRADIATION TYPE HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS Oct 27, 2022 Pending
Array ( [id] => 20540522 [patent_doc_number] => 12557611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Semiconductor on insulator structure comprising a buried high resistivity layer [patent_app_type] => utility [patent_app_number] => 18/047401 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047401 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047401
Semiconductor on insulator structure comprising a buried high resistivity layer Oct 17, 2022 Issued
Array ( [id] => 18158034 [patent_doc_number] => 20230024625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => ALUMINUM NITRIDE SINTERED BODY AND MEMBER FOR SEMICONDUCTOR MANUFACUTING APPARATUS COMPRISING SAME [patent_app_type] => utility [patent_app_number] => 17/938134 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/938134
Aluminum nitride sintered body and member for semiconductor manufacturing apparatus comprising same Oct 4, 2022 Issued
Array ( [id] => 18991095 [patent_doc_number] => 20240063064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => INTEGRATED DIPOLE REGION FOR TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/891923 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891923
INTEGRATED DIPOLE REGION FOR TRANSISTOR Aug 18, 2022 Pending
Array ( [id] => 18024546 [patent_doc_number] => 20220376045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => HIGH VOLTAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/882817 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882817
HIGH VOLTAGE DEVICE Aug 7, 2022 Pending
Array ( [id] => 18967430 [patent_doc_number] => 11901210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => 3D semiconductor device and structure with memory [patent_app_type] => utility [patent_app_number] => 17/880653 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 345 [patent_no_of_words] => 80044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880653
3D semiconductor device and structure with memory Aug 3, 2022 Issued
Array ( [id] => 17993267 [patent_doc_number] => 20220359304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => HIGH VOLTAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/874503 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874503
High voltage devices Jul 26, 2022 Issued
Array ( [id] => 20807379 [patent_doc_number] => 12672298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/815007 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 32 [patent_no_of_words] => 3451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815007
Semiconductor device and method Jul 25, 2022 Issued
Array ( [id] => 18024361 [patent_doc_number] => 20220375860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => STRUCTURE AND METHOD FOR TRANSISTORS HAVING BACKSIDE POWER RAILS [patent_app_type] => utility [patent_app_number] => 17/815119 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815119
Structure and method for transistors having backside power rails Jul 25, 2022 Issued
Array ( [id] => 20831255 [patent_doc_number] => 12684854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Interconnect structure having a multi-deck conductive feature and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/814998 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814998
Interconnect structure having a multi-deck conductive feature and method of forming the same Jul 25, 2022 Issued
Array ( [id] => 20853206 [patent_doc_number] => 12690258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-21 [patent_title] => Dipole patterning for CMOS devices [patent_app_type] => utility [patent_app_number] => 17/873787 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 34 [patent_no_of_words] => 4242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873787
Dipole Patterning for CMOS Devices Jul 25, 2022 Issued
Array ( [id] => 17993029 [patent_doc_number] => 20220359066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/814731 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814731 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814731
Semiconductor Device and Method Jul 24, 2022 Pending
Array ( [id] => 17993656 [patent_doc_number] => 20220359693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/814725 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814725
Semiconductor Device and Method Jul 24, 2022 Pending
Array ( [id] => 17993264 [patent_doc_number] => 20220359301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Dual Dopant Source/Drain Regions and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 17/869558 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869558
Dual Dopant Source/Drain Regions and Methods of Forming Same Jul 19, 2022 Pending
Array ( [id] => 17986304 [patent_doc_number] => 20220352341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MITIGATION OF TIME DEPENDENT DIELECTRIC BREAKDOWN [patent_app_type] => utility [patent_app_number] => 17/813700 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813700
MITIGATION OF TIME DEPENDENT DIELECTRIC BREAKDOWN Jul 19, 2022 Pending
Array ( [id] => 19221460 [patent_doc_number] => 20240186164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => WAFER HOLDER AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/799267 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799267 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/799267
WAFER HOLDER AND METHOD FOR OPERATING THE SAME Jul 14, 2022 Abandoned
Array ( [id] => 18865861 [patent_doc_number] => 20230420298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MULTI-PATHWAY ROUTING VIA THROUGH HOLE [patent_app_type] => utility [patent_app_number] => 17/851999 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851999
MULTI-PATHWAY ROUTING VIA THROUGH HOLE Jun 27, 2022 Pending
Array ( [id] => 20612835 [patent_doc_number] => 12588455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Dopant diffusion with short high temperature anneal pulses [patent_app_type] => utility [patent_app_number] => 17/842381 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6131 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842381
Dopant diffusion with short high temperature anneal pulses Jun 15, 2022 Issued
Array ( [id] => 18124465 [patent_doc_number] => 20230010077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/804169 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804169
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE May 25, 2022 Abandoned
Array ( [id] => 17840724 [patent_doc_number] => 20220278030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/747629 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747629
Semiconductor device May 17, 2022 Issued
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