
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5688387
[patent_doc_number] => 20060286702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-21
[patent_title] => 'METHOD OF MANUFACTURING A TRANSPARENT ELEMENT INCLUDING TRANSPARENT ELECTRODES'
[patent_app_type] => utility
[patent_app_number] => 11/424700
[patent_app_country] => US
[patent_app_date] => 2006-06-16
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[pdf_file] => publications/A1/0286/20060286702.pdf
[firstpage_image] =>[orig_patent_app_number] => 11424700
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424700 | Method of manufacturing a transparent element including transparent electrodes | Jun 15, 2006 | Issued |
Array
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[patent_doc_number] => 07741209
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[patent_issue_date] => 2010-06-22
[patent_title] => 'Contact structure of semiconductor device and method for fabricating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/423054 | Contact structure of semiconductor device and method for fabricating the same | Jun 7, 2006 | Issued |
Array
(
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[patent_doc_number] => 07514331
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[patent_issue_date] => 2009-04-07
[patent_title] => 'Method of manufacturing gate sidewalls that avoids recessing'
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[patent_app_number] => 11/422952
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/422952 | Method of manufacturing gate sidewalls that avoids recessing | Jun 7, 2006 | Issued |
Array
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[patent_issue_date] => 2006-10-19
[patent_title] => 'Method for manufacturing semiconductor device and semiconductor device'
[patent_app_type] => utility
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[patent_app_country] => US
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Array
(
[id] => 5010954
[patent_doc_number] => 20070281433
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[patent_issue_date] => 2007-12-06
[patent_title] => 'A METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT'
[patent_app_type] => utility
[patent_app_number] => 11/422221
[patent_app_country] => US
[patent_app_date] => 2006-06-05
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[firstpage_image] =>[orig_patent_app_number] => 11422221
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/422221 | Method for reducing dislocation threading using a suppression implant | Jun 4, 2006 | Issued |
Array
(
[id] => 5754159
[patent_doc_number] => 20060223308
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[patent_issue_date] => 2006-10-05
[patent_title] => 'APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/421672
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421672 | APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | May 31, 2006 | Abandoned |
Array
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[patent_title] => 'Method for fabricating semiconductor device with bulb shaped recess gate pattern'
[patent_app_type] => utility
[patent_app_number] => 11/411891
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[firstpage_image] =>[orig_patent_app_number] => 11411891
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/411891 | Method for fabricating semiconductor device with bulb shaped recess gate pattern | Apr 26, 2006 | Issued |
Array
(
[id] => 583526
[patent_doc_number] => 07446003
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[patent_issue_date] => 2008-11-04
[patent_title] => 'Manufacturing process for lateral power MOS transistors'
[patent_app_type] => utility
[patent_app_number] => 11/413961
[patent_app_country] => US
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[pdf_file] => patents/07/446/07446003.pdf
[firstpage_image] =>[orig_patent_app_number] => 11413961
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/413961 | Manufacturing process for lateral power MOS transistors | Apr 26, 2006 | Issued |
Array
(
[id] => 5210553
[patent_doc_number] => 20070249137
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[patent_issue_date] => 2007-10-25
[patent_title] => 'Method and system for wafer backside alignment'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/409582 | Method and system for wafer backside alignment | Apr 23, 2006 | Issued |
Array
(
[id] => 817044
[patent_doc_number] => 07410852
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[patent_issue_date] => 2008-08-12
[patent_title] => 'Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors'
[patent_app_type] => utility
[patent_app_number] => 11/408522
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/408522 | Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors | Apr 20, 2006 | Issued |
Array
(
[id] => 5616903
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[patent_title] => 'Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/407561 | Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device | Apr 18, 2006 | Issued |
Array
(
[id] => 582255
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[patent_title] => 'Method for effectively removing polysilicon nodule defects'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/402082 | Method for effectively removing polysilicon nodule defects | Apr 10, 2006 | Issued |
Array
(
[id] => 797949
[patent_doc_number] => 07427536
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[patent_title] => 'High density stepped, non-planar nitride read only memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/399761 | High density stepped, non-planar nitride read only memory | Apr 6, 2006 | Issued |
Array
(
[id] => 7691990
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[patent_title] => 'Method for forming thermal stable silicide using surface plasma treatment'
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Array
(
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Array
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