Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5688387 [patent_doc_number] => 20060286702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'METHOD OF MANUFACTURING A TRANSPARENT ELEMENT INCLUDING TRANSPARENT ELECTRODES' [patent_app_type] => utility [patent_app_number] => 11/424700 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2711 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286702.pdf [firstpage_image] =>[orig_patent_app_number] => 11424700 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424700
Method of manufacturing a transparent element including transparent electrodes Jun 15, 2006 Issued
Array ( [id] => 83537 [patent_doc_number] => 07741209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Contact structure of semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/423054 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2940 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741209.pdf [firstpage_image] =>[orig_patent_app_number] => 11423054 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/423054
Contact structure of semiconductor device and method for fabricating the same Jun 7, 2006 Issued
Array ( [id] => 326560 [patent_doc_number] => 07514331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method of manufacturing gate sidewalls that avoids recessing' [patent_app_type] => utility [patent_app_number] => 11/422952 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3978 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514331.pdf [firstpage_image] =>[orig_patent_app_number] => 11422952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422952
Method of manufacturing gate sidewalls that avoids recessing Jun 7, 2006 Issued
Array ( [id] => 5851322 [patent_doc_number] => 20060234513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Method for manufacturing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/447962 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7432 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20060234513.pdf [firstpage_image] =>[orig_patent_app_number] => 11447962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/447962
Method for manufacturing semiconductor device and semiconductor device Jun 6, 2006 Issued
Array ( [id] => 5010954 [patent_doc_number] => 20070281433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'A METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT' [patent_app_type] => utility [patent_app_number] => 11/422221 [patent_app_country] => US [patent_app_date] => 2006-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281433.pdf [firstpage_image] =>[orig_patent_app_number] => 11422221 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422221
Method for reducing dislocation threading using a suppression implant Jun 4, 2006 Issued
Array ( [id] => 5754159 [patent_doc_number] => 20060223308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/421672 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4424 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20060223308.pdf [firstpage_image] =>[orig_patent_app_number] => 11421672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421672
APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME May 31, 2006 Abandoned
Array ( [id] => 5022968 [patent_doc_number] => 20070148934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method for fabricating semiconductor device with bulb shaped recess gate pattern' [patent_app_type] => utility [patent_app_number] => 11/411891 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2429 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148934.pdf [firstpage_image] =>[orig_patent_app_number] => 11411891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/411891
Method for fabricating semiconductor device with bulb shaped recess gate pattern Apr 26, 2006 Issued
Array ( [id] => 583526 [patent_doc_number] => 07446003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Manufacturing process for lateral power MOS transistors' [patent_app_type] => utility [patent_app_number] => 11/413961 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3636 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446003.pdf [firstpage_image] =>[orig_patent_app_number] => 11413961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413961
Manufacturing process for lateral power MOS transistors Apr 26, 2006 Issued
Array ( [id] => 5210553 [patent_doc_number] => 20070249137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method and system for wafer backside alignment' [patent_app_type] => utility [patent_app_number] => 11/409582 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249137.pdf [firstpage_image] =>[orig_patent_app_number] => 11409582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409582
Method and system for wafer backside alignment Apr 23, 2006 Issued
Array ( [id] => 817044 [patent_doc_number] => 07410852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors' [patent_app_type] => utility [patent_app_number] => 11/408522 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4280 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410852.pdf [firstpage_image] =>[orig_patent_app_number] => 11408522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/408522
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors Apr 20, 2006 Issued
Array ( [id] => 5616903 [patent_doc_number] => 20060186435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/407561 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13895 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186435.pdf [firstpage_image] =>[orig_patent_app_number] => 11407561 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407561
Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device Apr 18, 2006 Issued
Array ( [id] => 582255 [patent_doc_number] => 07449413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Method for effectively removing polysilicon nodule defects' [patent_app_type] => utility [patent_app_number] => 11/402082 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3601 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449413.pdf [firstpage_image] =>[orig_patent_app_number] => 11402082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/402082
Method for effectively removing polysilicon nodule defects Apr 10, 2006 Issued
Array ( [id] => 797949 [patent_doc_number] => 07427536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'High density stepped, non-planar nitride read only memory' [patent_app_type] => utility [patent_app_number] => 11/399761 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427536.pdf [firstpage_image] =>[orig_patent_app_number] => 11399761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/399761
High density stepped, non-planar nitride read only memory Apr 6, 2006 Issued
Array ( [id] => 7691990 [patent_doc_number] => 20070232043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method for forming thermal stable silicide using surface plasma treatment' [patent_app_type] => utility [patent_app_number] => 11/395212 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2145 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232043.pdf [firstpage_image] =>[orig_patent_app_number] => 11395212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/395212
Method for forming thermal stable silicide using surface plasma treatment Apr 2, 2006 Abandoned
Array ( [id] => 5622925 [patent_doc_number] => 20060261430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Integrated layer stack arrangement, optical sensor and method for producing an integrated layer stack arrangement' [patent_app_type] => utility [patent_app_number] => 11/391613 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261430.pdf [firstpage_image] =>[orig_patent_app_number] => 11391613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/391613
Integrated layer stack arrangement, optical sensor and method for producing an integrated layer stack arrangement Mar 27, 2006 Issued
Array ( [id] => 315185 [patent_doc_number] => 07525155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'High voltage transistor structure for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/387573 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4305 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525155.pdf [firstpage_image] =>[orig_patent_app_number] => 11387573 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387573
High voltage transistor structure for semiconductor device Mar 22, 2006 Issued
Array ( [id] => 5874542 [patent_doc_number] => 20060166445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Methods of fabricating multiple sets of field effect transistors' [patent_app_type] => utility [patent_app_number] => 11/386167 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2793 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166445.pdf [firstpage_image] =>[orig_patent_app_number] => 11386167 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386167
Methods of fabricating multiple sets of field effect transistors Mar 20, 2006 Issued
Array ( [id] => 7593266 [patent_doc_number] => 07651934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Process for electroless copper deposition' [patent_app_type] => utility [patent_app_number] => 11/385037 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 9054 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/651/07651934.pdf [firstpage_image] =>[orig_patent_app_number] => 11385037 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385037
Process for electroless copper deposition Mar 19, 2006 Issued
Array ( [id] => 307321 [patent_doc_number] => 07531387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-12 [patent_title] => 'Flip chip mounting method and bump forming method' [patent_app_type] => utility [patent_app_number] => 11/887332 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 11012 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531387.pdf [firstpage_image] =>[orig_patent_app_number] => 11887332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/887332
Flip chip mounting method and bump forming method Mar 15, 2006 Issued
Array ( [id] => 307319 [patent_doc_number] => 07531385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-12 [patent_title] => 'Flip chip mounting method and method for connecting substrates' [patent_app_type] => utility [patent_app_number] => 11/887331 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7558 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531385.pdf [firstpage_image] =>[orig_patent_app_number] => 11887331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/887331
Flip chip mounting method and method for connecting substrates Mar 15, 2006 Issued
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