
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4502604
[patent_doc_number] => RE042232
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2011-03-22
[patent_title] => 'RF chipset architecture'
[patent_app_type] => reissue
[patent_app_number] => 11/376700
[patent_app_country] => US
[patent_app_date] => 2006-03-15
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[pdf_file] => patents/RE/042/RE042232.pdf
[firstpage_image] =>[orig_patent_app_number] => 11376700
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/376700 | RF chipset architecture | Mar 14, 2006 | Issued |
Array
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[patent_doc_number] => 20070218669
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[patent_issue_date] => 2007-09-20
[patent_title] => 'Method of forming a semiconductor device and structure thereof'
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[patent_title] => 'Manufacturing a semiconductive device using a controlled atomic layer removal process'
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Array
(
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[patent_issue_date] => 2006-07-13
[patent_title] => 'Manufacturing method which prevents abnormal gate oxidation'
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Array
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[patent_issue_date] => 2010-07-20
[patent_title] => 'Scalable photovoltaic cell and solar panel manufacturing with improved wiring'
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Array
(
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[patent_issue_date] => 2007-08-16
[patent_title] => 'CMOS Gate Structures Fabricated By Selective Oxidation'
[patent_app_type] => utility
[patent_app_number] => 11/307671
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Array
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[patent_title] => 'Method of filling a high aspect ratio trench isolation region and resulting structure'
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Array
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[patent_title] => 'Semiconductor interconnect having adjacent reservoir for bonding and method for formation'
[patent_app_type] => utility
[patent_app_number] => 11/339132
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Array
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[id] => 5924806
[patent_doc_number] => 20060241236
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[patent_title] => 'Electromagnetic radiation attenuation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/338527 | Electromagnetic radiation attenuation | Jan 23, 2006 | Issued |
Array
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[id] => 356587
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[patent_title] => 'Device and method for fabricating double-sided SOI wafer scale package with optical through via connections'
[patent_app_type] => utility
[patent_app_number] => 11/325105
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Array
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[patent_title] => 'Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same'
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Array
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Array
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