Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4502604 [patent_doc_number] => RE042232 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-03-22 [patent_title] => 'RF chipset architecture' [patent_app_type] => reissue [patent_app_number] => 11/376700 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042232.pdf [firstpage_image] =>[orig_patent_app_number] => 11376700 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376700
RF chipset architecture Mar 14, 2006 Issued
Array ( [id] => 4977436 [patent_doc_number] => 20070218669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method of forming a semiconductor device and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/376412 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218669.pdf [firstpage_image] =>[orig_patent_app_number] => 11376412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376412
Method of forming a semiconductor device and structure thereof Mar 14, 2006 Issued
Array ( [id] => 348767 [patent_doc_number] => 07494882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Manufacturing a semiconductive device using a controlled atomic layer removal process' [patent_app_type] => utility [patent_app_number] => 11/373662 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3617 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494882.pdf [firstpage_image] =>[orig_patent_app_number] => 11373662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/373662
Manufacturing a semiconductive device using a controlled atomic layer removal process Mar 9, 2006 Issued
Array ( [id] => 5694312 [patent_doc_number] => 20060154459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Manufacturing method which prevents abnormal gate oxidation' [patent_app_type] => utility [patent_app_number] => 11/367435 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5998 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154459.pdf [firstpage_image] =>[orig_patent_app_number] => 11367435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367435
Manufacturing method which prevents abnormal gate oxidation Mar 5, 2006 Issued
Array ( [id] => 63609 [patent_doc_number] => 07759158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Scalable photovoltaic cell and solar panel manufacturing with improved wiring' [patent_app_type] => utility [patent_app_number] => 11/367068 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5578 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759158.pdf [firstpage_image] =>[orig_patent_app_number] => 11367068 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367068
Scalable photovoltaic cell and solar panel manufacturing with improved wiring Mar 2, 2006 Issued
Array ( [id] => 5069611 [patent_doc_number] => 20070190713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'CMOS Gate Structures Fabricated By Selective Oxidation' [patent_app_type] => utility [patent_app_number] => 11/307671 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20070190713.pdf [firstpage_image] =>[orig_patent_app_number] => 11307671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/307671
CMOS gate structures fabricated by selective oxidation Feb 15, 2006 Issued
Array ( [id] => 5157498 [patent_doc_number] => 20070170542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method of filling a high aspect ratio trench isolation region and resulting structure' [patent_app_type] => utility [patent_app_number] => 11/339565 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2963 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170542.pdf [firstpage_image] =>[orig_patent_app_number] => 11339565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339565
Method of filling a high aspect ratio trench isolation region and resulting structure Jan 25, 2006 Abandoned
Array ( [id] => 5157540 [patent_doc_number] => 20070170584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Semiconductor interconnect having adjacent reservoir for bonding and method for formation' [patent_app_type] => utility [patent_app_number] => 11/339132 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170584.pdf [firstpage_image] =>[orig_patent_app_number] => 11339132 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339132
Semiconductor interconnect having adjacent reservoir for bonding and method for formation Jan 24, 2006 Issued
Array ( [id] => 5924806 [patent_doc_number] => 20060241236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Electromagnetic radiation attenuation' [patent_app_type] => utility [patent_app_number] => 11/338527 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11433 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20060241236.pdf [firstpage_image] =>[orig_patent_app_number] => 11338527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/338527
Electromagnetic radiation attenuation Jan 23, 2006 Issued
Array ( [id] => 356587 [patent_doc_number] => 07489025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Device and method for fabricating double-sided SOI wafer scale package with optical through via connections' [patent_app_type] => utility [patent_app_number] => 11/325105 [patent_app_country] => US [patent_app_date] => 2006-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 38 [patent_no_of_words] => 6330 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489025.pdf [firstpage_image] =>[orig_patent_app_number] => 11325105 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/325105
Device and method for fabricating double-sided SOI wafer scale package with optical through via connections Jan 3, 2006 Issued
Array ( [id] => 5747926 [patent_doc_number] => 20060110857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 11/324330 [patent_app_country] => US [patent_app_date] => 2006-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12041 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20060110857.pdf [firstpage_image] =>[orig_patent_app_number] => 11324330 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324330
Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same Jan 3, 2006 Issued
Array ( [id] => 5677920 [patent_doc_number] => 20060183276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/322658 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 23045 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20060183276.pdf [firstpage_image] =>[orig_patent_app_number] => 11322658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322658
Method of manufacturing a semiconductor device Jan 2, 2006 Issued
Array ( [id] => 5863157 [patent_doc_number] => 20060097287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/319534 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5850 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097287.pdf [firstpage_image] =>[orig_patent_app_number] => 11319534 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319534
Semiconductor device and manufacturing method thereof Dec 28, 2005 Abandoned
Array ( [id] => 363417 [patent_doc_number] => 07482228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method of forming a MOS transistor with a litho-less gate' [patent_app_type] => utility [patent_app_number] => 11/305994 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 2233 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482228.pdf [firstpage_image] =>[orig_patent_app_number] => 11305994 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305994
Method of forming a MOS transistor with a litho-less gate Dec 18, 2005 Issued
Array ( [id] => 5649076 [patent_doc_number] => 20060134811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Semiconductor processing apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/305201 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134811.pdf [firstpage_image] =>[orig_patent_app_number] => 11305201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305201
Semiconductor processing apparatus and method Dec 18, 2005 Issued
Array ( [id] => 5863206 [patent_doc_number] => 20060097336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'High-powered light emitting device with improved thermal properties' [patent_app_type] => utility [patent_app_number] => 11/311961 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4438 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097336.pdf [firstpage_image] =>[orig_patent_app_number] => 11311961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/311961
High-powered light emitting device with improved thermal properties Dec 18, 2005 Issued
Array ( [id] => 311444 [patent_doc_number] => 07528476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument' [patent_app_type] => utility [patent_app_number] => 11/305471 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 8997 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528476.pdf [firstpage_image] =>[orig_patent_app_number] => 11305471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305471
Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument Dec 15, 2005 Issued
Array ( [id] => 581708 [patent_doc_number] => 07456479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method for fabricating a probing pad of an integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 11/306062 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1458 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456479.pdf [firstpage_image] =>[orig_patent_app_number] => 11306062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/306062
Method for fabricating a probing pad of an integrated circuit chip Dec 14, 2005 Issued
Array ( [id] => 270451 [patent_doc_number] => 07563687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/302971 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 14 [patent_no_of_words] => 2507 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563687.pdf [firstpage_image] =>[orig_patent_app_number] => 11302971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302971
Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit Dec 13, 2005 Issued
Array ( [id] => 5832169 [patent_doc_number] => 20060243999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'LED package structure and method of packaging the same' [patent_app_type] => utility [patent_app_number] => 11/302127 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12571 [patent_no_of_claims] => 110 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20060243999.pdf [firstpage_image] =>[orig_patent_app_number] => 11302127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302127
LED package structure and method of packaging the same Dec 13, 2005 Issued
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