Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 233122 [patent_doc_number] => 07598549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Semiconductor device having a silicon layer in a gate electrode' [patent_app_type] => utility [patent_app_number] => 11/299731 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5789 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598549.pdf [firstpage_image] =>[orig_patent_app_number] => 11299731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/299731
Semiconductor device having a silicon layer in a gate electrode Dec 12, 2005 Issued
Array ( [id] => 5141903 [patent_doc_number] => 20070004119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'CMOS device with dual polycide gates and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/299501 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3458 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004119.pdf [firstpage_image] =>[orig_patent_app_number] => 11299501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/299501
CMOS device with dual polycide gates and method of manufacturing the same Dec 11, 2005 Issued
Array ( [id] => 380063 [patent_doc_number] => 07309637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method to enhance device performance with selective stress relief' [patent_app_type] => utility [patent_app_number] => 11/299542 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3480 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309637.pdf [firstpage_image] =>[orig_patent_app_number] => 11299542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/299542
Method to enhance device performance with selective stress relief Dec 11, 2005 Issued
Array ( [id] => 5645844 [patent_doc_number] => 20060131576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Semiconductor device having overlay measurement mark and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/296921 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6961 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131576.pdf [firstpage_image] =>[orig_patent_app_number] => 11296921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296921
Semiconductor device having overlay measurement mark and method of fabricating the same Dec 7, 2005 Issued
Array ( [id] => 5253486 [patent_doc_number] => 20070134942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Hafnium tantalum titanium oxide films' [patent_app_type] => utility [patent_app_number] => 11/297741 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9628 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20070134942.pdf [firstpage_image] =>[orig_patent_app_number] => 11297741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297741
Hafnium tantalum titanium oxide films Dec 7, 2005 Issued
Array ( [id] => 5079792 [patent_doc_number] => 20070123016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Device with gaps for capacitance reduction' [patent_app_type] => utility [patent_app_number] => 11/291411 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4476 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20070123016.pdf [firstpage_image] =>[orig_patent_app_number] => 11291411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/291411
Device with gaps for capacitance reduction Nov 29, 2005 Issued
Array ( [id] => 5863137 [patent_doc_number] => 20060097267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Silicon carbide semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/268612 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097267.pdf [firstpage_image] =>[orig_patent_app_number] => 11268612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268612
Silicon carbide semiconductor device and method for manufacturing the same Nov 7, 2005 Issued
Array ( [id] => 817051 [patent_doc_number] => 07410859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Stressed MOS device and method for its fabrication' [patent_app_type] => utility [patent_app_number] => 11/269241 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3197 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410859.pdf [firstpage_image] =>[orig_patent_app_number] => 11269241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269241
Stressed MOS device and method for its fabrication Nov 6, 2005 Issued
Array ( [id] => 5718441 [patent_doc_number] => 20060071214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Process for manufacturing a semiconductor device, a semiconductor device and a high-frequency circuit' [patent_app_type] => utility [patent_app_number] => 11/242792 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3534 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071214.pdf [firstpage_image] =>[orig_patent_app_number] => 11242792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242792
Process for manufacturing a semiconductor device, a semiconductor device and a high-frequency circuit Oct 4, 2005 Issued
Array ( [id] => 565046 [patent_doc_number] => 07465621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-16 [patent_title] => 'Method of fabricating a switching regulator with a high-side p-type device' [patent_app_type] => utility [patent_app_number] => 11/232516 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 53 [patent_no_of_words] => 9791 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465621.pdf [firstpage_image] =>[orig_patent_app_number] => 11232516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/232516
Method of fabricating a switching regulator with a high-side p-type device Sep 20, 2005 Issued
Array ( [id] => 4745792 [patent_doc_number] => 20080090394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Temperature Synthesis of Hexagonal Zns Nanocrystals as Well as Derivatives with Different Transition Metal Dopants Using the Said Method' [patent_app_type] => utility [patent_app_number] => 11/574372 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090394.pdf [firstpage_image] =>[orig_patent_app_number] => 11574372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/574372
Temperature Synthesis of Hexagonal Zns Nanocrystals as Well as Derivatives with Different Transition Metal Dopants Using the Said Method Aug 23, 2005 Abandoned
Array ( [id] => 830093 [patent_doc_number] => 07399646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Magnetic devices and techniques for formation thereof' [patent_app_type] => utility [patent_app_number] => 11/209951 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4663 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/399/07399646.pdf [firstpage_image] =>[orig_patent_app_number] => 11209951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209951
Magnetic devices and techniques for formation thereof Aug 22, 2005 Issued
Array ( [id] => 576355 [patent_doc_number] => 07456062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method of forming a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/209871 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6596 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456062.pdf [firstpage_image] =>[orig_patent_app_number] => 11209871 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209871
Method of forming a semiconductor device Aug 22, 2005 Issued
Array ( [id] => 7247981 [patent_doc_number] => 20050272208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique' [patent_app_type] => utility [patent_app_number] => 11/204552 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2888 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20050272208.pdf [firstpage_image] =>[orig_patent_app_number] => 11204552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204552
Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique Aug 15, 2005 Abandoned
Array ( [id] => 411538 [patent_doc_number] => 07282403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Temperature stable metal nitride gate electrode' [patent_app_type] => utility [patent_app_number] => 11/203952 [patent_app_country] => US [patent_app_date] => 2005-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 5016 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282403.pdf [firstpage_image] =>[orig_patent_app_number] => 11203952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/203952
Temperature stable metal nitride gate electrode Aug 14, 2005 Issued
Array ( [id] => 5828285 [patent_doc_number] => 20060063314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Field effect transistor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/203402 [patent_app_country] => US [patent_app_date] => 2005-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6414 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063314.pdf [firstpage_image] =>[orig_patent_app_number] => 11203402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/203402
Field effect transistor and method of manufacturing the same Aug 14, 2005 Abandoned
Array ( [id] => 467330 [patent_doc_number] => 07235468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-26 [patent_title] => 'FinFET device with reduced DIBL' [patent_app_type] => utility [patent_app_number] => 11/201038 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3983 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/235/07235468.pdf [firstpage_image] =>[orig_patent_app_number] => 11201038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201038
FinFET device with reduced DIBL Aug 9, 2005 Issued
Array ( [id] => 5049042 [patent_doc_number] => 20070029586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Multi-channel transistor structure and method of making thereof' [patent_app_type] => utility [patent_app_number] => 11/199482 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7132 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20070029586.pdf [firstpage_image] =>[orig_patent_app_number] => 11199482 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199482
Multi-channel transistor structure and method of making thereof Aug 7, 2005 Issued
Array ( [id] => 5688443 [patent_doc_number] => 20060286758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Super anneal for process induced strain modulation' [patent_app_type] => utility [patent_app_number] => 11/199011 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3748 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286758.pdf [firstpage_image] =>[orig_patent_app_number] => 11199011 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199011
Super anneal for process induced strain modulation Aug 7, 2005 Issued
Array ( [id] => 7053842 [patent_doc_number] => 20050275014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Integration method of a semiconductor device having a recessed gate electrode' [patent_app_type] => utility [patent_app_number] => 11/195525 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2499 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275014.pdf [firstpage_image] =>[orig_patent_app_number] => 11195525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195525
Integration method of a semiconductor device having a recessed gate electrode Jul 31, 2005 Abandoned
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