Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5205133 [patent_doc_number] => 20070026615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method of forming a FINFET structure' [patent_app_type] => utility [patent_app_number] => 11/190411 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026615.pdf [firstpage_image] =>[orig_patent_app_number] => 11190411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/190411
Method of forming a FINFET structure Jul 26, 2005 Issued
Array ( [id] => 5763160 [patent_doc_number] => 20060017099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'MOS transistor having a recessed gate electrode and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/184801 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20060017099.pdf [firstpage_image] =>[orig_patent_app_number] => 11184801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/184801
MOS transistor having a recessed gate electrode and fabrication method thereof Jul 19, 2005 Issued
Array ( [id] => 902974 [patent_doc_number] => 07335557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Semiconductor device of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/185006 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 69 [patent_no_of_words] => 10052 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335557.pdf [firstpage_image] =>[orig_patent_app_number] => 11185006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185006
Semiconductor device of non-volatile memory Jul 19, 2005 Issued
Array ( [id] => 5881014 [patent_doc_number] => 20060030097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed' [patent_app_type] => utility [patent_app_number] => 11/183651 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20060030097.pdf [firstpage_image] =>[orig_patent_app_number] => 11183651 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183651
Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed Jul 17, 2005 Issued
Array ( [id] => 5242372 [patent_doc_number] => 20070020867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Buried stress isolation for high-performance CMOS technology' [patent_app_type] => utility [patent_app_number] => 11/183062 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3828 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020867.pdf [firstpage_image] =>[orig_patent_app_number] => 11183062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183062
Buried stress isolation for high-performance CMOS technology Jul 14, 2005 Issued
Array ( [id] => 833439 [patent_doc_number] => 07396728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Methods of improving drive currents by employing strain inducing STI liners' [patent_app_type] => utility [patent_app_number] => 11/170501 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4790 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/396/07396728.pdf [firstpage_image] =>[orig_patent_app_number] => 11170501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170501
Methods of improving drive currents by employing strain inducing STI liners Jun 28, 2005 Issued
Array ( [id] => 6923422 [patent_doc_number] => 20050236677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Semiconductor device layout and channeling implant process' [patent_app_type] => utility [patent_app_number] => 11/170576 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20050236677.pdf [firstpage_image] =>[orig_patent_app_number] => 11170576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170576
Semiconductor device layout and channeling implant process Jun 27, 2005 Issued
Array ( [id] => 341578 [patent_doc_number] => 07501336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Metal gate device with reduced oxidation of a high-k gate dielectric' [patent_app_type] => utility [patent_app_number] => 11/158621 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501336.pdf [firstpage_image] =>[orig_patent_app_number] => 11158621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158621
Metal gate device with reduced oxidation of a high-k gate dielectric Jun 20, 2005 Issued
Array ( [id] => 6963952 [patent_doc_number] => 20050230849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Injection molding device with outside air inlet part' [patent_app_type] => utility [patent_app_number] => 11/153542 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17159 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230849.pdf [firstpage_image] =>[orig_patent_app_number] => 11153542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153542
Injection molding device with outside air inlet part Jun 15, 2005 Issued
Array ( [id] => 5688421 [patent_doc_number] => 20060286736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Method for forming an electronic device' [patent_app_type] => utility [patent_app_number] => 11/152931 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286736.pdf [firstpage_image] =>[orig_patent_app_number] => 11152931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152931
Method for forming an electronic device Jun 14, 2005 Issued
Array ( [id] => 5022868 [patent_doc_number] => 20070148834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Laser irradiation apparatus and laser irradiation method' [patent_app_type] => utility [patent_app_number] => 10/584472 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7591 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148834.pdf [firstpage_image] =>[orig_patent_app_number] => 10584472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/584472
Laser irradiation apparatus and laser irradiation method Jun 14, 2005 Issued
Array ( [id] => 843483 [patent_doc_number] => 07387926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Method for manufacturing CMOS image sensor' [patent_app_type] => utility [patent_app_number] => 11/148212 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 3138 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/387/07387926.pdf [firstpage_image] =>[orig_patent_app_number] => 11148212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148212
Method for manufacturing CMOS image sensor Jun 8, 2005 Issued
Array ( [id] => 6952332 [patent_doc_number] => 20050227427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Formation of standard voltage threshold and low voltage threshold MOSFET devices' [patent_app_type] => utility [patent_app_number] => 11/146812 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5449 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20050227427.pdf [firstpage_image] =>[orig_patent_app_number] => 11146812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/146812
Formation of standard voltage threshold and low voltage threshold MOSFET devices Jun 6, 2005 Issued
Array ( [id] => 7019543 [patent_doc_number] => 20050221562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Method for manufacturing semiconductor device having thick insulating layer under gate side walls' [patent_app_type] => utility [patent_app_number] => 11/136419 [patent_app_country] => US [patent_app_date] => 2005-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5940 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221562.pdf [firstpage_image] =>[orig_patent_app_number] => 11136419 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/136419
Method for manufacturing semiconductor device having thick insulating layer under gate side walls May 24, 2005 Issued
Array ( [id] => 229188 [patent_doc_number] => 07602003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Semiconductor device structure for reducing hot carrier effect of MOS transistor' [patent_app_type] => utility [patent_app_number] => 10/908071 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1678 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602003.pdf [firstpage_image] =>[orig_patent_app_number] => 10908071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908071
Semiconductor device structure for reducing hot carrier effect of MOS transistor Apr 26, 2005 Issued
Array ( [id] => 5851253 [patent_doc_number] => 20060234444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'SPLIT GATE FLASH MEMORY CELL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 10/907781 [patent_app_country] => US [patent_app_date] => 2005-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6184 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20060234444.pdf [firstpage_image] =>[orig_patent_app_number] => 10907781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907781
Split gate flash memory cell and manufacturing method thereof Apr 14, 2005 Issued
Array ( [id] => 754307 [patent_doc_number] => 07018895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Nonvolatile memory cell with multiple floating gates formed after the select gate' [patent_app_type] => utility [patent_app_number] => 11/102066 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 48 [patent_no_of_words] => 6991 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018895.pdf [firstpage_image] =>[orig_patent_app_number] => 11102066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/102066
Nonvolatile memory cell with multiple floating gates formed after the select gate Apr 7, 2005 Issued
Array ( [id] => 6925661 [patent_doc_number] => 20050238916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Transition metal complex and light-emitting device' [patent_app_type] => utility [patent_app_number] => 11/101555 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12995 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20050238916.pdf [firstpage_image] =>[orig_patent_app_number] => 11101555 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/101555
Transition metal complex and light-emitting device Apr 7, 2005 Issued
Array ( [id] => 397602 [patent_doc_number] => 07294571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Concave pattern formation method and method for forming semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/098371 [patent_app_country] => US [patent_app_date] => 2005-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 67 [patent_no_of_words] => 12947 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294571.pdf [firstpage_image] =>[orig_patent_app_number] => 11098371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098371
Concave pattern formation method and method for forming semiconductor device Apr 4, 2005 Issued
Array ( [id] => 7162127 [patent_doc_number] => 20050199966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Dual work function semiconductor structure with borderless contact and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/098103 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4284 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20050199966.pdf [firstpage_image] =>[orig_patent_app_number] => 11098103 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098103
Dual work function semiconductor structure with borderless contact and method of fabricating the same Apr 3, 2005 Issued
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