Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 377033 [patent_doc_number] => 07312133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/075022 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 6413 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312133.pdf [firstpage_image] =>[orig_patent_app_number] => 11075022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/075022
Method of manufacturing semiconductor device Mar 7, 2005 Issued
Array ( [id] => 525392 [patent_doc_number] => 07183169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-27 [patent_title] => 'Method and arrangement for reducing source/drain resistance with epitaxial growth' [patent_app_type] => utility [patent_app_number] => 11/072312 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2225 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183169.pdf [firstpage_image] =>[orig_patent_app_number] => 11072312 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/072312
Method and arrangement for reducing source/drain resistance with epitaxial growth Mar 6, 2005 Issued
Array ( [id] => 7111308 [patent_doc_number] => 20050208764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Integrated circuit metal silicide method' [patent_app_type] => utility [patent_app_number] => 11/073982 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2614 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208764.pdf [firstpage_image] =>[orig_patent_app_number] => 11073982 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073982
Integrated circuit metal silicide method Mar 6, 2005 Issued
Array ( [id] => 472519 [patent_doc_number] => 07229914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Wiring layer structure for ferroelectric capacitor' [patent_app_type] => utility [patent_app_number] => 11/065582 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 7766 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/229/07229914.pdf [firstpage_image] =>[orig_patent_app_number] => 11065582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065582
Wiring layer structure for ferroelectric capacitor Feb 24, 2005 Issued
Array ( [id] => 1075575 [patent_doc_number] => RE040965 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method of forming low-resistance contact electrodes in semiconductor devices' [patent_app_type] => reissue [patent_app_number] => 11/065718 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2597 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040965.pdf [firstpage_image] =>[orig_patent_app_number] => 11065718 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065718
Method of forming low-resistance contact electrodes in semiconductor devices Feb 23, 2005 Issued
Array ( [id] => 7236183 [patent_doc_number] => 20050139930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Strained dislocation-free channels for CMOS and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/061445 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3947 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139930.pdf [firstpage_image] =>[orig_patent_app_number] => 11061445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061445
Strained dislocation-free channels for CMOS and method of manufacture Feb 21, 2005 Issued
Array ( [id] => 91910 [patent_doc_number] => 07732263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/590022 [patent_app_country] => US [patent_app_date] => 2005-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 50 [patent_no_of_words] => 17593 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732263.pdf [firstpage_image] =>[orig_patent_app_number] => 10590022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/590022
Semiconductor device Feb 20, 2005 Issued
Array ( [id] => 6981188 [patent_doc_number] => 20050151256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Freestanding multilayer IC wiring structure' [patent_app_type] => utility [patent_app_number] => 11/060802 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151256.pdf [firstpage_image] =>[orig_patent_app_number] => 11060802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060802
Freestanding multilayer IC wiring structure Feb 17, 2005 Abandoned
Array ( [id] => 7074880 [patent_doc_number] => 20050148148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method of forming a source/drain and a transistor employing the same' [patent_app_type] => utility [patent_app_number] => 11/059956 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6537 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148148.pdf [firstpage_image] =>[orig_patent_app_number] => 11059956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059956
Method of forming a source/drain and a transistor employing the same Feb 16, 2005 Issued
Array ( [id] => 7002466 [patent_doc_number] => 20050167779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Process for manufacturing vertically insulated structural components on SOI material of various thickness' [patent_app_type] => utility [patent_app_number] => 11/045382 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3344 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167779.pdf [firstpage_image] =>[orig_patent_app_number] => 11045382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/045382
Process for manufacturing vertically insulated structural components on SOI material of various thickness Jan 30, 2005 Issued
Array ( [id] => 5667169 [patent_doc_number] => 20060172519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Method for eliminating polycide voids through nitrogen implantation' [patent_app_type] => utility [patent_app_number] => 11/044212 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1342 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20060172519.pdf [firstpage_image] =>[orig_patent_app_number] => 11044212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044212
Method for eliminating polycide voids through nitrogen implantation Jan 27, 2005 Issued
Array ( [id] => 7597706 [patent_doc_number] => 07618871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Method for the production of a bipolar transistor comprising an improved base terminal' [patent_app_type] => utility [patent_app_number] => 10/593141 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4388 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/618/07618871.pdf [firstpage_image] =>[orig_patent_app_number] => 10593141 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/593141
Method for the production of a bipolar transistor comprising an improved base terminal Jan 18, 2005 Issued
Array ( [id] => 5596374 [patent_doc_number] => 20060160291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer' [patent_app_type] => utility [patent_app_number] => 11/039542 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2902 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20060160291.pdf [firstpage_image] =>[orig_patent_app_number] => 11039542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/039542
Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer Jan 18, 2005 Issued
Array ( [id] => 6996859 [patent_doc_number] => 20050136637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Indium oxide conductive film structures' [patent_app_type] => utility [patent_app_number] => 11/039543 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4020 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136637.pdf [firstpage_image] =>[orig_patent_app_number] => 11039543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/039543
Indium oxide conductive film structures Jan 18, 2005 Issued
Array ( [id] => 879774 [patent_doc_number] => 07354821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Methods of fabricating trench capacitors with insulating layer collars in undercut regions' [patent_app_type] => utility [patent_app_number] => 11/037626 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 6996 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/354/07354821.pdf [firstpage_image] =>[orig_patent_app_number] => 11037626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037626
Methods of fabricating trench capacitors with insulating layer collars in undercut regions Jan 17, 2005 Issued
Array ( [id] => 6912481 [patent_doc_number] => 20050176239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Method for making contact making connections' [patent_app_type] => utility [patent_app_number] => 11/033471 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2961 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176239.pdf [firstpage_image] =>[orig_patent_app_number] => 11033471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033471
Method for fabricating contact-making connections Jan 11, 2005 Issued
Array ( [id] => 7178732 [patent_doc_number] => 20050124106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Reverse metal process for creating a metal silicide transistor gate structure' [patent_app_type] => utility [patent_app_number] => 11/033525 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5671 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20050124106.pdf [firstpage_image] =>[orig_patent_app_number] => 11033525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033525
Reverse metal process for creating a metal silicide transistor gate structure Jan 11, 2005 Issued
Array ( [id] => 7144343 [patent_doc_number] => 20050118824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Multi-step chemical mechanical polishing of a gate area in a FinFET' [patent_app_type] => utility [patent_app_number] => 11/030191 [patent_app_country] => US [patent_app_date] => 2005-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3483 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20050118824.pdf [firstpage_image] =>[orig_patent_app_number] => 11030191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030191
Multi-step chemical mechanical polishing of a gate area in a FinFET Jan 6, 2005 Issued
Array ( [id] => 534457 [patent_doc_number] => 07172959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Method for forming dual damascene interconnection in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/024842 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1681 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/172/07172959.pdf [firstpage_image] =>[orig_patent_app_number] => 11024842 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024842
Method for forming dual damascene interconnection in semiconductor device Dec 29, 2004 Issued
Array ( [id] => 518075 [patent_doc_number] => 07189629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method for isolating semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/024632 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3414 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/189/07189629.pdf [firstpage_image] =>[orig_patent_app_number] => 11024632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024632
Method for isolating semiconductor devices Dec 29, 2004 Issued
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