Mary Ann Calabrese

Array ( [id] => 6983504 [patent_doc_number] => 20050153574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Very low dielectric constant plasma-enhanced CVD films' [patent_app_type] => utility [patent_app_number] => 11/001761 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153574.pdf [firstpage_image] =>[orig_patent_app_number] => 11001761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 865187 [patent_doc_number] => RE040275 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-04-29 [patent_title] => 'Method for producing a memory cell' [patent_app_type] => reissue [patent_app_number] => 11/000495 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2467 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040275.pdf [firstpage_image] =>[orig_patent_app_number] => 11000495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6918211 [patent_doc_number] => 20050095772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/998920 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17522 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095772.pdf [firstpage_image] =>[orig_patent_app_number] => 10998920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 480151 [patent_doc_number] => 07224049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 10/988551 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 12062 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224049.pdf [firstpage_image] =>[orig_patent_app_number] => 10988551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6912465 [patent_doc_number] => 20050176223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Substrate processing method' [patent_app_type] => utility [patent_app_number] => 10/988561 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5574 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176223.pdf [firstpage_image] =>[orig_patent_app_number] => 10988561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5776856 [patent_doc_number] => 20060105496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Device and method for fabricating double-sided SOI wafer scale package with through via connections' [patent_app_type] => utility [patent_app_number] => 10/990252 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3612 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20060105496.pdf [firstpage_image] =>[orig_patent_app_number] => 10990252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 609452 [patent_doc_number] => 07151018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-19 [patent_title] => 'Method and apparatus for transistor sidewall salicidation' [patent_app_type] => utility [patent_app_number] => 10/989911 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151018.pdf [firstpage_image] =>[orig_patent_app_number] => 10989911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5865656 [patent_doc_number] => 20060099787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method for damascene formation using plug materials having varied etching rates' [patent_app_type] => utility [patent_app_number] => 10/983681 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3945 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099787.pdf [firstpage_image] =>[orig_patent_app_number] => 10983681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5865657 [patent_doc_number] => 20060099788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Injection molded metal bonding tray for integrated circuit device fabrication' [patent_app_type] => utility [patent_app_number] => 10/984042 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4431 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20060099788.pdf [firstpage_image] =>[orig_patent_app_number] => 10984042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7161791 [patent_doc_number] => 20050084986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Semiconductor test board having laser patterned conductors' [patent_app_type] => utility [patent_app_number] => 10/983111 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5862 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20050084986.pdf [firstpage_image] =>[orig_patent_app_number] => 10983111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 654642 [patent_doc_number] => 07109127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/981662 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 5779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109127.pdf [firstpage_image] =>[orig_patent_app_number] => 10981662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7003783 [patent_doc_number] => 20050169096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'PAA- based etchant, methods of using same, and resultant structures' [patent_app_type] => utility [patent_app_number] => 10/976161 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 9927 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20050169096.pdf [firstpage_image] =>[orig_patent_app_number] => 10976161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6918249 [patent_doc_number] => 20050095810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Manufacturing method of thin film device substrate' [patent_app_type] => utility [patent_app_number] => 10/974932 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 8280 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095810.pdf [firstpage_image] =>[orig_patent_app_number] => 10974932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7127471 [patent_doc_number] => 20050059215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Semiconductor device with dual gate oxides' [patent_app_type] => utility [patent_app_number] => 10/973852 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3376 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20050059215.pdf [firstpage_image] =>[orig_patent_app_number] => 10973852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 740812 [patent_doc_number] => 07029925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'FeRAM capacitor stack etch' [patent_app_type] => utility [patent_app_number] => 10/968721 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 20747 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/029/07029925.pdf [firstpage_image] =>[orig_patent_app_number] => 10968721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 675741 [patent_doc_number] => 07087479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method of forming integrated circuit contacts' [patent_app_type] => utility [patent_app_number] => 10/962048 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4116 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087479.pdf [firstpage_image] =>[orig_patent_app_number] => 10962048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7161874 [patent_doc_number] => 20050085010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Wireless communication medium and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/959082 [patent_app_country] => US [patent_app_date] => 2004-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5473 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20050085010.pdf [firstpage_image] =>[orig_patent_app_number] => 10959082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5720899 [patent_doc_number] => 20060073674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Strained gettering layers for semiconductor processes' [patent_app_type] => utility [patent_app_number] => 10/956481 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6680 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20060073674.pdf [firstpage_image] =>[orig_patent_app_number] => 10956481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5720913 [patent_doc_number] => 20060073688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'GATE STACKS' [patent_app_type] => utility [patent_app_number] => 10/711742 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20060073688.pdf [firstpage_image] =>[orig_patent_app_number] => 10711742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 626996 [patent_doc_number] => 07135379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Isolation trench perimeter implant for threshold voltage control' [patent_app_type] => utility [patent_app_number] => 10/955658 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2615 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135379.pdf [firstpage_image] =>[orig_patent_app_number] => 10955658 [rel_patent_id] =>[rel_patent_doc_number] =>)