
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5637538
[patent_doc_number] => 20060068511
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[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'CMP process metrology test structures'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956452 | CMP process metrology test structures | Sep 29, 2004 | Issued |
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[patent_issue_date] => 2006-07-25
[patent_title] => 'Method for fabricating memory cells and memory cell array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/952371 | Method for fabricating memory cells and memory cell array | Sep 28, 2004 | Issued |
Array
(
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[patent_doc_number] => 20060068575
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[patent_issue_date] => 2006-03-30
[patent_title] => 'GATE ELECTRODE FORMING METHODS USING CONDUCTIVE HARD MASK'
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[patent_app_number] => 10/711642
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711642 | Gate electrode forming methods using conductive hard mask | Sep 28, 2004 | Issued |
| 10/956016 | FABRICATING METHOD FOR SEMICONDUCTOR PACKAGE | Sep 28, 2004 | Abandoned |
Array
(
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[patent_title] => 'Method for forming a semiconductor device having a strained channel and a heterojunction source/drain'
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[patent_app_number] => 10/954121
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Array
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[patent_title] => 'Method of forming self-aligned contact pads of non-straight type semiconductor memory device'
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Array
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[patent_title] => 'HEMT device and method of making'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938602 | HEMT device and method of making | Sep 12, 2004 | Issued |
Array
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[patent_title] => 'Structure and method for latchup suppression utilizing trench and masked sub-collector implantation'
[patent_app_type] => utility
[patent_app_number] => 10/711300
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711300 | Structure and method for latchup suppression utilizing trench and masked sub-collector implantation | Sep 8, 2004 | Issued |
Array
(
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[patent_title] => 'Methods for forming porous insulator structures on semiconductor devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/933061 | Methods for forming porous insulator structures on semiconductor devices | Aug 31, 2004 | Issued |
Array
(
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[patent_title] => 'Formation of standard voltage threshold and low voltge threshold MOSFET devices'
[patent_app_type] => utility
[patent_app_number] => 10/931891
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Array
(
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[patent_title] => 'SILICON OXIDE GAPFILL DEPOSITION USING LIQUID PRECURSORS'
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[patent_app_number] => 10/931742
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931742 | Silicon oxide gapfill deposition using liquid precursors | Aug 31, 2004 | Issued |
Array
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[id] => 7033857
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[patent_title] => 'Passivation processes for use with metallization techniques'
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Array
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Array
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[patent_title] => 'Laser based method and device for forming spacer structures for packaging optical reflection devices'
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Array
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Array
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Array
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