Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5637538 [patent_doc_number] => 20060068511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'CMP process metrology test structures' [patent_app_type] => utility [patent_app_number] => 10/956452 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2867 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20060068511.pdf [firstpage_image] =>[orig_patent_app_number] => 10956452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956452
CMP process metrology test structures Sep 29, 2004 Issued
Array ( [id] => 682477 [patent_doc_number] => 07081383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Method for fabricating memory cells and memory cell array' [patent_app_type] => utility [patent_app_number] => 10/952371 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3478 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081383.pdf [firstpage_image] =>[orig_patent_app_number] => 10952371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952371
Method for fabricating memory cells and memory cell array Sep 28, 2004 Issued
Array ( [id] => 5637602 [patent_doc_number] => 20060068575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'GATE ELECTRODE FORMING METHODS USING CONDUCTIVE HARD MASK' [patent_app_type] => utility [patent_app_number] => 10/711642 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20060068575.pdf [firstpage_image] =>[orig_patent_app_number] => 10711642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711642
Gate electrode forming methods using conductive hard mask Sep 28, 2004 Issued
10/956016 FABRICATING METHOD FOR SEMICONDUCTOR PACKAGE Sep 28, 2004 Abandoned
Array ( [id] => 754331 [patent_doc_number] => 07018901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Method for forming a semiconductor device having a strained channel and a heterojunction source/drain' [patent_app_type] => utility [patent_app_number] => 10/954121 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6117 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018901.pdf [firstpage_image] =>[orig_patent_app_number] => 10954121 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954121
Method for forming a semiconductor device having a strained channel and a heterojunction source/drain Sep 28, 2004 Issued
Array ( [id] => 6939287 [patent_doc_number] => 20050112850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/944933 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 23041 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112850.pdf [firstpage_image] =>[orig_patent_app_number] => 10944933 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944933
Method of manufacturing a semiconductor device Sep 20, 2004 Issued
Array ( [id] => 7116779 [patent_doc_number] => 20050070080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method of forming self-aligned contact pads of non-straight type semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/944151 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4217 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070080.pdf [firstpage_image] =>[orig_patent_app_number] => 10944151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944151
Method of forming self-aligned contact pads of non-straight type semiconductor memory device Sep 15, 2004 Issued
Array ( [id] => 7607621 [patent_doc_number] => 07098093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'HEMT device and method of making' [patent_app_type] => utility [patent_app_number] => 10/938602 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 2528 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098093.pdf [firstpage_image] =>[orig_patent_app_number] => 10938602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/938602
HEMT device and method of making Sep 12, 2004 Issued
Array ( [id] => 956514 [patent_doc_number] => 06956266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Structure and method for latchup suppression utilizing trench and masked sub-collector implantation' [patent_app_type] => utility [patent_app_number] => 10/711300 [patent_app_country] => US [patent_app_date] => 2004-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 7184 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/956/06956266.pdf [firstpage_image] =>[orig_patent_app_number] => 10711300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711300
Structure and method for latchup suppression utilizing trench and masked sub-collector implantation Sep 8, 2004 Issued
Array ( [id] => 7033885 [patent_doc_number] => 20050032395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Methods for forming porous insulator structures on semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/933061 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7885 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032395.pdf [firstpage_image] =>[orig_patent_app_number] => 10933061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/933061
Methods for forming porous insulator structures on semiconductor devices Aug 31, 2004 Issued
Array ( [id] => 7154653 [patent_doc_number] => 20050026352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Formation of standard voltage threshold and low voltge threshold MOSFET devices' [patent_app_type] => utility [patent_app_number] => 10/931891 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026352.pdf [firstpage_image] =>[orig_patent_app_number] => 10931891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931891
Formation of standard voltage threshold and low voltage threshold MOSFET devices Aug 31, 2004 Issued
Array ( [id] => 5903668 [patent_doc_number] => 20060046508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'SILICON OXIDE GAPFILL DEPOSITION USING LIQUID PRECURSORS' [patent_app_type] => utility [patent_app_number] => 10/931742 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6070 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046508.pdf [firstpage_image] =>[orig_patent_app_number] => 10931742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931742
Silicon oxide gapfill deposition using liquid precursors Aug 31, 2004 Issued
Array ( [id] => 7033857 [patent_doc_number] => 20050032367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Passivation processes for use with metallization techniques' [patent_app_type] => utility [patent_app_number] => 10/931355 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5219 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032367.pdf [firstpage_image] =>[orig_patent_app_number] => 10931355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931355
Passivation processes for use with metallization techniques Aug 30, 2004 Issued
Array ( [id] => 668422 [patent_doc_number] => 07094663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/929782 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3287 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/094/07094663.pdf [firstpage_image] =>[orig_patent_app_number] => 10929782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929782
Semiconductor device and method of manufacturing the same Aug 30, 2004 Issued
Array ( [id] => 5903540 [patent_doc_number] => 20060046429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Laser based method and device for forming spacer structures for packaging optical reflection devices' [patent_app_type] => utility [patent_app_number] => 10/930312 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3961 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046429.pdf [firstpage_image] =>[orig_patent_app_number] => 10930312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930312
Laser based method and device for forming spacer structures for packaging optical reflection devices Aug 29, 2004 Issued
Array ( [id] => 7083328 [patent_doc_number] => 20050048708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/923045 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 17438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20050048708.pdf [firstpage_image] =>[orig_patent_app_number] => 10923045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923045
Method of manufacturing a semiconductor device Aug 22, 2004 Issued
Array ( [id] => 767169 [patent_doc_number] => 07009250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'FinFET device with reduced DIBL' [patent_app_type] => utility [patent_app_number] => 10/923191 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3963 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009250.pdf [firstpage_image] =>[orig_patent_app_number] => 10923191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923191
FinFET device with reduced DIBL Aug 19, 2004 Issued
Array ( [id] => 959292 [patent_doc_number] => 06954240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Method of producing polarizing plate, and liquid crystal display comprising the polarizing plate' [patent_app_type] => utility [patent_app_number] => 10/921189 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6231 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954240.pdf [firstpage_image] =>[orig_patent_app_number] => 10921189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/921189
Method of producing polarizing plate, and liquid crystal display comprising the polarizing plate Aug 18, 2004 Issued
Array ( [id] => 7025686 [patent_doc_number] => 20050020080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Method of depositing a diffusion barrier layer and a metal conductive layer' [patent_app_type] => utility [patent_app_number] => 10/922052 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7556 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20050020080.pdf [firstpage_image] =>[orig_patent_app_number] => 10922052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/922052
Method of depositing a diffusion barrier layer and a metal conductive layer Aug 17, 2004 Abandoned
Array ( [id] => 698900 [patent_doc_number] => 07067378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Methods of fabricating multiple sets of field effect transistors' [patent_app_type] => utility [patent_app_number] => 10/914822 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2735 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067378.pdf [firstpage_image] =>[orig_patent_app_number] => 10914822 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914822
Methods of fabricating multiple sets of field effect transistors Aug 8, 2004 Issued
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