Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7612870 [patent_doc_number] => 06902964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure' [patent_app_type] => utility [patent_app_number] => 10/909112 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6950 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/902/06902964.pdf [firstpage_image] =>[orig_patent_app_number] => 10909112 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909112
Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure Jul 29, 2004 Issued
Array ( [id] => 7120334 [patent_doc_number] => 20050012163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Apparatus and manufacturing process of carbon nanotube gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 10/901091 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1724 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012163.pdf [firstpage_image] =>[orig_patent_app_number] => 10901091 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901091
Apparatus and manufacturing process of carbon nanotube gate field effect transistor Jul 28, 2004 Issued
Array ( [id] => 5793669 [patent_doc_number] => 20060014350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR TRANSISTOR DEVICE HAVING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 10/710521 [patent_app_country] => US [patent_app_date] => 2004-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014350.pdf [firstpage_image] =>[orig_patent_app_number] => 10710521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710521
METHOD FOR FABRICATING A SEMICONDUCTOR TRANSISTOR DEVICE HAVING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS Jul 17, 2004 Abandoned
Array ( [id] => 5793644 [patent_doc_number] => 20060014325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method of assembling a semiconductor component and apparatus therefor' [patent_app_type] => utility [patent_app_number] => 10/891648 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3798 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014325.pdf [firstpage_image] =>[orig_patent_app_number] => 10891648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891648
Method of assembling a semiconductor component and apparatus therefor Jul 14, 2004 Issued
Array ( [id] => 634131 [patent_doc_number] => 07129187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films' [patent_app_type] => utility [patent_app_number] => 10/891301 [patent_app_country] => US [patent_app_date] => 2004-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4162 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129187.pdf [firstpage_image] =>[orig_patent_app_number] => 10891301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891301
Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films Jul 13, 2004 Issued
Array ( [id] => 701431 [patent_doc_number] => 07064000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Methods of chemically assembled electronic nanotechnology circuit fabrication' [patent_app_type] => utility [patent_app_number] => 10/889294 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 13651 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064000.pdf [firstpage_image] =>[orig_patent_app_number] => 10889294 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889294
Methods of chemically assembled electronic nanotechnology circuit fabrication Jul 11, 2004 Issued
Array ( [id] => 7236465 [patent_doc_number] => 20050139965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/883322 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4880 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139965.pdf [firstpage_image] =>[orig_patent_app_number] => 10883322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883322
Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same Jun 29, 2004 Issued
Array ( [id] => 496994 [patent_doc_number] => 07208407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Flash memory cells with reduced distances between cell elements' [patent_app_type] => utility [patent_app_number] => 10/881042 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3144 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208407.pdf [firstpage_image] =>[orig_patent_app_number] => 10881042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881042
Flash memory cells with reduced distances between cell elements Jun 29, 2004 Issued
Array ( [id] => 6978060 [patent_doc_number] => 20050287778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'METHOD FOR FORMING AN ULTRA-SHALLOW JUNCTION IN A SEMICONDUCTOR SUBSTRATE USING A NUCLEAR STOPPING LAYER' [patent_app_type] => utility [patent_app_number] => 10/710241 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1917 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287778.pdf [firstpage_image] =>[orig_patent_app_number] => 10710241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710241
Method for forming an ultra-shallow junction in a semiconductor substrate using a nuclear stopping layer Jun 28, 2004 Issued
Array ( [id] => 7203569 [patent_doc_number] => 20050042778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'System and method for determining the temperature of a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 10/875788 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4316 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20050042778.pdf [firstpage_image] =>[orig_patent_app_number] => 10875788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875788
System and method for determining the temperature of a semiconductor wafer Jun 24, 2004 Issued
Array ( [id] => 6939272 [patent_doc_number] => 20050112835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method for fabricating transistor of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/874932 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2977 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112835.pdf [firstpage_image] =>[orig_patent_app_number] => 10874932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874932
Method for fabricating transistor of semiconductor device Jun 22, 2004 Issued
Array ( [id] => 6931335 [patent_doc_number] => 20050282370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'SELECTIVE SALICIDATION METHODS' [patent_app_type] => utility [patent_app_number] => 10/710131 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282370.pdf [firstpage_image] =>[orig_patent_app_number] => 10710131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710131
Selective salicidation methods Jun 20, 2004 Issued
Array ( [id] => 754259 [patent_doc_number] => 07018876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Transistor with vertical dielectric structure' [patent_app_type] => utility [patent_app_number] => 10/871772 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2934 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018876.pdf [firstpage_image] =>[orig_patent_app_number] => 10871772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/871772
Transistor with vertical dielectric structure Jun 17, 2004 Issued
Array ( [id] => 4469535 [patent_doc_number] => 07943505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Advanced VLSI metallization' [patent_app_type] => utility [patent_app_number] => 10/871242 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2078 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/943/07943505.pdf [firstpage_image] =>[orig_patent_app_number] => 10871242 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/871242
Advanced VLSI metallization Jun 17, 2004 Issued
Array ( [id] => 7314273 [patent_doc_number] => 20040222466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Implanted asymmetric doped polysilicon gate FinFet' [patent_app_type] => new [patent_app_number] => 10/869624 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3006 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222466.pdf [firstpage_image] =>[orig_patent_app_number] => 10869624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869624
Implanted asymmetric doped polysilicon gate FinFET Jun 15, 2004 Issued
Array ( [id] => 7019608 [patent_doc_number] => 20050221627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Method for producing optical film' [patent_app_type] => utility [patent_app_number] => 10/867671 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2559 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221627.pdf [firstpage_image] =>[orig_patent_app_number] => 10867671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867671
Method for producing optical film Jun 15, 2004 Issued
Array ( [id] => 7253495 [patent_doc_number] => 20050142773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Structure and method for protecting substrate of an active area' [patent_app_type] => utility [patent_app_number] => 10/864371 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1818 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142773.pdf [firstpage_image] =>[orig_patent_app_number] => 10864371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/864371
Structure and method for protecting substrate of an active area Jun 9, 2004 Abandoned
Array ( [id] => 7253417 [patent_doc_number] => 20040259388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Method for heat treating a semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/863352 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3272 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20040259388.pdf [firstpage_image] =>[orig_patent_app_number] => 10863352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863352
Method for heat treating a semiconductor wafer Jun 8, 2004 Issued
Array ( [id] => 7252937 [patent_doc_number] => 20040259306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method' [patent_app_type] => new [patent_app_number] => 10/855402 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6840 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20040259306.pdf [firstpage_image] =>[orig_patent_app_number] => 10855402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/855402
Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method May 27, 2004 Issued
Array ( [id] => 7252927 [patent_doc_number] => 20040259304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => new [patent_app_number] => 10/854162 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5759 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20040259304.pdf [firstpage_image] =>[orig_patent_app_number] => 10854162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854162
Semiconductor device manufacturing method May 26, 2004 Issued
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