
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7612870
[patent_doc_number] => 06902964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure'
[patent_app_type] => utility
[patent_app_number] => 10/909112
[patent_app_country] => US
[patent_app_date] => 2004-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6950
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[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/902/06902964.pdf
[firstpage_image] =>[orig_patent_app_number] => 10909112
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/909112 | Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure | Jul 29, 2004 | Issued |
Array
(
[id] => 7120334
[patent_doc_number] => 20050012163
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Apparatus and manufacturing process of carbon nanotube gate field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 10/901091
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20050012163.pdf
[firstpage_image] =>[orig_patent_app_number] => 10901091
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901091 | Apparatus and manufacturing process of carbon nanotube gate field effect transistor | Jul 28, 2004 | Issued |
Array
(
[id] => 5793669
[patent_doc_number] => 20060014350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR TRANSISTOR DEVICE HAVING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS'
[patent_app_type] => utility
[patent_app_number] => 10/710521
[patent_app_country] => US
[patent_app_date] => 2004-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 1668
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20060014350.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710521
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710521 | METHOD FOR FABRICATING A SEMICONDUCTOR TRANSISTOR DEVICE HAVING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS | Jul 17, 2004 | Abandoned |
Array
(
[id] => 5793644
[patent_doc_number] => 20060014325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Method of assembling a semiconductor component and apparatus therefor'
[patent_app_type] => utility
[patent_app_number] => 10/891648
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3798
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[pdf_file] => publications/A1/0014/20060014325.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891648 | Method of assembling a semiconductor component and apparatus therefor | Jul 14, 2004 | Issued |
Array
(
[id] => 634131
[patent_doc_number] => 07129187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films'
[patent_app_type] => utility
[patent_app_number] => 10/891301
[patent_app_country] => US
[patent_app_date] => 2004-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4162
[patent_no_of_claims] => 56
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/129/07129187.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891301
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891301 | Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films | Jul 13, 2004 | Issued |
Array
(
[id] => 701431
[patent_doc_number] => 07064000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Methods of chemically assembled electronic nanotechnology circuit fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/889294
[patent_app_country] => US
[patent_app_date] => 2004-07-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/064/07064000.pdf
[firstpage_image] =>[orig_patent_app_number] => 10889294
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/889294 | Methods of chemically assembled electronic nanotechnology circuit fabrication | Jul 11, 2004 | Issued |
Array
(
[id] => 7236465
[patent_doc_number] => 20050139965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/883322
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4880
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[pdf_file] => publications/A1/0139/20050139965.pdf
[firstpage_image] =>[orig_patent_app_number] => 10883322
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/883322 | Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same | Jun 29, 2004 | Issued |
Array
(
[id] => 496994
[patent_doc_number] => 07208407
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Flash memory cells with reduced distances between cell elements'
[patent_app_type] => utility
[patent_app_number] => 10/881042
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3144
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[pdf_file] => patents/07/208/07208407.pdf
[firstpage_image] =>[orig_patent_app_number] => 10881042
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/881042 | Flash memory cells with reduced distances between cell elements | Jun 29, 2004 | Issued |
Array
(
[id] => 6978060
[patent_doc_number] => 20050287778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'METHOD FOR FORMING AN ULTRA-SHALLOW JUNCTION IN A SEMICONDUCTOR SUBSTRATE USING A NUCLEAR STOPPING LAYER'
[patent_app_type] => utility
[patent_app_number] => 10/710241
[patent_app_country] => US
[patent_app_date] => 2004-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0287/20050287778.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710241
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710241 | Method for forming an ultra-shallow junction in a semiconductor substrate using a nuclear stopping layer | Jun 28, 2004 | Issued |
Array
(
[id] => 7203569
[patent_doc_number] => 20050042778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'System and method for determining the temperature of a semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 10/875788
[patent_app_country] => US
[patent_app_date] => 2004-06-25
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[firstpage_image] =>[orig_patent_app_number] => 10875788
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/875788 | System and method for determining the temperature of a semiconductor wafer | Jun 24, 2004 | Issued |
Array
(
[id] => 6939272
[patent_doc_number] => 20050112835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Method for fabricating transistor of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/874932
[patent_app_country] => US
[patent_app_date] => 2004-06-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/874932 | Method for fabricating transistor of semiconductor device | Jun 22, 2004 | Issued |
Array
(
[id] => 6931335
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[patent_issue_date] => 2005-12-22
[patent_title] => 'SELECTIVE SALICIDATION METHODS'
[patent_app_type] => utility
[patent_app_number] => 10/710131
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10710131
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710131 | Selective salicidation methods | Jun 20, 2004 | Issued |
Array
(
[id] => 754259
[patent_doc_number] => 07018876
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[patent_title] => 'Transistor with vertical dielectric structure'
[patent_app_type] => utility
[patent_app_number] => 10/871772
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[firstpage_image] =>[orig_patent_app_number] => 10871772
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/871772 | Transistor with vertical dielectric structure | Jun 17, 2004 | Issued |
Array
(
[id] => 4469535
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[patent_kind] => B2
[patent_issue_date] => 2011-05-17
[patent_title] => 'Advanced VLSI metallization'
[patent_app_type] => utility
[patent_app_number] => 10/871242
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Array
(
[id] => 7314273
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[patent_title] => 'Implanted asymmetric doped polysilicon gate FinFet'
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[firstpage_image] =>[orig_patent_app_number] => 10869624
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/869624 | Implanted asymmetric doped polysilicon gate FinFET | Jun 15, 2004 | Issued |
Array
(
[id] => 7019608
[patent_doc_number] => 20050221627
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[patent_issue_date] => 2005-10-06
[patent_title] => 'Method for producing optical film'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/867671 | Method for producing optical film | Jun 15, 2004 | Issued |
Array
(
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[patent_title] => 'Structure and method for protecting substrate of an active area'
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Array
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Array
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[firstpage_image] =>[orig_patent_app_number] => 10854162
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/854162 | Semiconductor device manufacturing method | May 26, 2004 | Issued |