Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 415547 [patent_doc_number] => 07279732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Enhanced atomic layer deposition' [patent_app_type] => utility [patent_app_number] => 10/854593 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10275 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279732.pdf [firstpage_image] =>[orig_patent_app_number] => 10854593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854593
Enhanced atomic layer deposition May 25, 2004 Issued
Array ( [id] => 630367 [patent_doc_number] => 07132327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Decoupled complementary mask patterning transfer method' [patent_app_type] => utility [patent_app_number] => 10/853701 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 5338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132327.pdf [firstpage_image] =>[orig_patent_app_number] => 10853701 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853701
Decoupled complementary mask patterning transfer method May 24, 2004 Issued
Array ( [id] => 531245 [patent_doc_number] => 07179758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics' [patent_app_type] => utility [patent_app_number] => 10/853771 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6627 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/179/07179758.pdf [firstpage_image] =>[orig_patent_app_number] => 10853771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853771
Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics May 24, 2004 Issued
Array ( [id] => 7221253 [patent_doc_number] => 20050260819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'REDUCED DIELECTRIC CONSTANT SPACER MATERIALS INTEGRATION FOR HIGH SPEED LOGIC GATES' [patent_app_type] => utility [patent_app_number] => 10/709652 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20050260819.pdf [firstpage_image] =>[orig_patent_app_number] => 10709652 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709652
Reduced dielectric constant spacer materials integration for high speed logic gates May 19, 2004 Issued
Array ( [id] => 7275802 [patent_doc_number] => 20040235253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same' [patent_app_type] => new [patent_app_number] => 10/849671 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4120 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20040235253.pdf [firstpage_image] =>[orig_patent_app_number] => 10849671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/849671
Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same May 18, 2004 Issued
Array ( [id] => 7291715 [patent_doc_number] => 20040211992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method for manufacturing and structure for transistors with reduced gate to contact spacing' [patent_app_type] => new [patent_app_number] => 10/846741 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4956 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20040211992.pdf [firstpage_image] =>[orig_patent_app_number] => 10846741 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/846741
Method for manufacturing and structure for transistors with reduced gate to contact spacing May 13, 2004 Issued
Array ( [id] => 6983421 [patent_doc_number] => 20050153491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Process of forming low-strain(relaxed) silicon geranium crystal layer' [patent_app_type] => utility [patent_app_number] => 10/838252 [patent_app_country] => US [patent_app_date] => 2004-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2748 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153491.pdf [firstpage_image] =>[orig_patent_app_number] => 10838252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/838252
Process of forming low-strain(relaxed) silicon geranium crystal layer May 4, 2004 Abandoned
Array ( [id] => 737109 [patent_doc_number] => 07033879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Semiconductor device having optimized shallow junction geometries and method for fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/835121 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5090 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/033/07033879.pdf [firstpage_image] =>[orig_patent_app_number] => 10835121 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835121
Semiconductor device having optimized shallow junction geometries and method for fabrication thereof Apr 28, 2004 Issued
Array ( [id] => 686595 [patent_doc_number] => 07078295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Self-aligned split-gate nonvolatile memory structure and a method of making the same' [patent_app_type] => utility [patent_app_number] => 10/834082 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5152 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078295.pdf [firstpage_image] =>[orig_patent_app_number] => 10834082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834082
Self-aligned split-gate nonvolatile memory structure and a method of making the same Apr 28, 2004 Issued
Array ( [id] => 655777 [patent_doc_number] => 07109555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method for providing short channel effect control using a silicide VSS line' [patent_app_type] => utility [patent_app_number] => 10/835341 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2199 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109555.pdf [firstpage_image] =>[orig_patent_app_number] => 10835341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835341
Method for providing short channel effect control using a silicide VSS line Apr 27, 2004 Issued
Array ( [id] => 686214 [patent_doc_number] => 07077929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Apparatus for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/835372 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4373 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/077/07077929.pdf [firstpage_image] =>[orig_patent_app_number] => 10835372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/835372
Apparatus for manufacturing a semiconductor device Apr 27, 2004 Issued
Array ( [id] => 7462852 [patent_doc_number] => 20040198071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Method of forming silicon oxide film and forming apparatus thereof' [patent_app_type] => new [patent_app_number] => 10/832502 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4653 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198071.pdf [firstpage_image] =>[orig_patent_app_number] => 10832502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832502
Method of forming silicon oxide film and forming apparatus thereof Apr 26, 2004 Issued
Array ( [id] => 7462452 [patent_doc_number] => 20040198004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Low voltage high performance semiconductor devices and methods' [patent_app_type] => new [patent_app_number] => 10/831192 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4254 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198004.pdf [firstpage_image] =>[orig_patent_app_number] => 10831192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831192
Low voltage high performance semiconductor devices and methods Apr 25, 2004 Issued
Array ( [id] => 7080585 [patent_doc_number] => 20050045965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Device having multiple silicide types and a method for its fabrication' [patent_app_type] => utility [patent_app_number] => 10/831021 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 8160 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045965.pdf [firstpage_image] =>[orig_patent_app_number] => 10831021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831021
Method for forming a device having multiple silicide types Apr 22, 2004 Issued
Array ( [id] => 7094792 [patent_doc_number] => 20050127435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method of forming self-aligned poly for embedded flash' [patent_app_type] => utility [patent_app_number] => 10/822505 [patent_app_country] => US [patent_app_date] => 2004-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8179 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127435.pdf [firstpage_image] =>[orig_patent_app_number] => 10822505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822505
Method of forming self-aligned poly for embedded flash Apr 11, 2004 Issued
Array ( [id] => 679633 [patent_doc_number] => 07084015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 10/822121 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5052 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084015.pdf [firstpage_image] =>[orig_patent_app_number] => 10822121 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822121
Semiconductor constructions Apr 8, 2004 Issued
Array ( [id] => 1021490 [patent_doc_number] => 06887764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method for producing a gate structure for an MOS transistor' [patent_app_type] => utility [patent_app_number] => 10/821251 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/887/06887764.pdf [firstpage_image] =>[orig_patent_app_number] => 10821251 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821251
Method for producing a gate structure for an MOS transistor Apr 7, 2004 Issued
Array ( [id] => 7108446 [patent_doc_number] => 20050205899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/820601 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2413 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20050205899.pdf [firstpage_image] =>[orig_patent_app_number] => 10820601 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820601
Method for fabricating semiconductor device Apr 6, 2004 Issued
Array ( [id] => 744668 [patent_doc_number] => 07026205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Method for manufacturing semiconductor device, including multiple heat treatment' [patent_app_type] => utility [patent_app_number] => 10/815931 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 8367 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026205.pdf [firstpage_image] =>[orig_patent_app_number] => 10815931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815931
Method for manufacturing semiconductor device, including multiple heat treatment Apr 1, 2004 Issued
Array ( [id] => 7420513 [patent_doc_number] => 20040183064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Single electron devices' [patent_app_type] => new [patent_app_number] => 10/814292 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2987 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183064.pdf [firstpage_image] =>[orig_patent_app_number] => 10814292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814292
Single electron devices Mar 31, 2004 Abandoned
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