Mary Ann Calabrese

Array ( [id] => 1110851 [patent_doc_number] => 06806116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'SnO2 ISFET device, manufacturing method, and methods and apparatus for use thereof' [patent_app_type] => B2 [patent_app_number] => 10/811801 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5184 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806116.pdf [firstpage_image] =>[orig_patent_app_number] => 10811801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7375445 [patent_doc_number] => 20040178459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Manufacturing method for a semiconductor device with reduced local current' [patent_app_type] => new [patent_app_number] => 10/809011 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4010 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178459.pdf [firstpage_image] =>[orig_patent_app_number] => 10809011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 754277 [patent_doc_number] => 07018882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon' [patent_app_type] => utility [patent_app_number] => 10/807931 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2049 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018882.pdf [firstpage_image] =>[orig_patent_app_number] => 10807931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7264069 [patent_doc_number] => 20040241946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Methods of fabricating a semiconductor substrate for reducing wafer warpage' [patent_app_type] => new [patent_app_number] => 10/806521 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4733 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241946.pdf [firstpage_image] =>[orig_patent_app_number] => 10806521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7089152 [patent_doc_number] => 20050009265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method of fabricating MOS transistor using total gate silicidation process' [patent_app_type] => utility [patent_app_number] => 10/806301 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4171 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009265.pdf [firstpage_image] =>[orig_patent_app_number] => 10806301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7442716 [patent_doc_number] => 20040185626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Semiconductor device with different lattice properties' [patent_app_type] => new [patent_app_number] => 10/801651 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5434 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185626.pdf [firstpage_image] =>[orig_patent_app_number] => 10801651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 732536 [patent_doc_number] => 07037767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Thin-film transistor, thin-film transistor sheet and their manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/801212 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 10337 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/037/07037767.pdf [firstpage_image] =>[orig_patent_app_number] => 10801212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1071876 [patent_doc_number] => 06841460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Anti-type dosage as LDD implant' [patent_app_type] => utility [patent_app_number] => 10/798992 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3429 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841460.pdf [firstpage_image] =>[orig_patent_app_number] => 10798992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 961079 [patent_doc_number] => 06951792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-04 [patent_title] => 'Dual-oxide transistors for the improvement of reliability and off-state leakage' [patent_app_type] => utility [patent_app_number] => 10/800221 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3851 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951792.pdf [firstpage_image] =>[orig_patent_app_number] => 10800221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 679647 [patent_doc_number] => 07084021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method of forming a structure wherein an electrode comprising a refractory metal is deposited' [patent_app_type] => utility [patent_app_number] => 10/797202 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4487 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084021.pdf [firstpage_image] =>[orig_patent_app_number] => 10797202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 993599 [patent_doc_number] => 06916698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'High performance CMOS device structure with mid-gap metal gate' [patent_app_type] => utility [patent_app_number] => 10/795672 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2359 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/916/06916698.pdf [firstpage_image] =>[orig_patent_app_number] => 10795672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 701485 [patent_doc_number] => 07064031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method for forming a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/793762 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 2779 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064031.pdf [firstpage_image] =>[orig_patent_app_number] => 10793762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 695037 [patent_doc_number] => 07071117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Semiconductor devices and methods for depositing a dielectric film' [patent_app_type] => utility [patent_app_number] => 10/788892 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6293 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071117.pdf [firstpage_image] =>[orig_patent_app_number] => 10788892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 698885 [patent_doc_number] => 07067370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method of manufacturing a MOS transistor of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/785268 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067370.pdf [firstpage_image] =>[orig_patent_app_number] => 10785268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7462437 [patent_doc_number] => 20040198002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Semiconductor device and method of manufacturing thereof' [patent_app_type] => new [patent_app_number] => 10/775236 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 15282 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198002.pdf [firstpage_image] =>[orig_patent_app_number] => 10775236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 785227 [patent_doc_number] => 06989314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Semiconductor structure and method of making same' [patent_app_type] => utility [patent_app_number] => 10/777721 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3915 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989314.pdf [firstpage_image] =>[orig_patent_app_number] => 10777721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253025 [patent_doc_number] => 20050142671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Low energy dose monitoring of implanter using implanted wafers' [patent_app_type] => utility [patent_app_number] => 10/773728 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3932 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142671.pdf [firstpage_image] =>[orig_patent_app_number] => 10773728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7212222 [patent_doc_number] => 20040154163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Method of forming a connecting conductor and wirings of a semiconductor chip' [patent_app_type] => new [patent_app_number] => 10/771451 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13918 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20040154163.pdf [firstpage_image] =>[orig_patent_app_number] => 10771451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1009340 [patent_doc_number] => 06900102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Methods of forming double gate electrodes using tunnel and trench' [patent_app_type] => utility [patent_app_number] => 10/773022 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 37 [patent_no_of_words] => 5342 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900102.pdf [firstpage_image] =>[orig_patent_app_number] => 10773022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7005282 [patent_doc_number] => 20050170595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT AND CHANNELING IMPLANT PROCESS' [patent_app_type] => utility [patent_app_number] => 10/768612 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4869 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170595.pdf [firstpage_image] =>[orig_patent_app_number] => 10768612 [rel_patent_id] =>[rel_patent_doc_number] =>)