
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 650933
[patent_doc_number] => 07112510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-26
[patent_title] => 'Methods for forming a device isolating barrier and methods for forming a gate electrode using the same'
[patent_app_type] => utility
[patent_app_number] => 10/764637
[patent_app_country] => US
[patent_app_date] => 2004-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 2075
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/112/07112510.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764637
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764637 | Methods for forming a device isolating barrier and methods for forming a gate electrode using the same | Jan 25, 2004 | Issued |
Array
(
[id] => 7677551
[patent_doc_number] => 20040152275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A MOSFET WITH NITRIDE SIDEWALLS'
[patent_app_type] => new
[patent_app_number] => 10/762361
[patent_app_country] => US
[patent_app_date] => 2004-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 6062
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 18
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20040152275.pdf
[firstpage_image] =>[orig_patent_app_number] => 10762361
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/762361 | Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls | Jan 22, 2004 | Issued |
Array
(
[id] => 1040553
[patent_doc_number] => 06869851
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-22
[patent_title] => 'Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps'
[patent_app_type] => utility
[patent_app_number] => 10/761438
[patent_app_country] => US
[patent_app_date] => 2004-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 7645
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/869/06869851.pdf
[firstpage_image] =>[orig_patent_app_number] => 10761438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/761438 | Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps | Jan 19, 2004 | Issued |
Array
(
[id] => 7039556
[patent_doc_number] => 20050158955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'METHOD AND APPARATUS TO INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 10/707842
[patent_app_country] => US
[patent_app_date] => 2004-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3081
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158955.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707842
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707842 | Method and apparatus to increase strain effect in a transistor channel | Jan 15, 2004 | Issued |
Array
(
[id] => 7039557
[patent_doc_number] => 20050158956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal'
[patent_app_type] => utility
[patent_app_number] => 10/759671
[patent_app_country] => US
[patent_app_date] => 2004-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1931
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20050158956.pdf
[firstpage_image] =>[orig_patent_app_number] => 10759671
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/759671 | Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal | Jan 15, 2004 | Issued |
Array
(
[id] => 6983425
[patent_doc_number] => 20050153495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Silicon - germanium virtual substrate and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/755501
[patent_app_country] => US
[patent_app_date] => 2004-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2332
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20050153495.pdf
[firstpage_image] =>[orig_patent_app_number] => 10755501
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/755501 | Silicon-germanium virtual substrate and method of fabricating the same | Jan 11, 2004 | Issued |
Array
(
[id] => 698902
[patent_doc_number] => 07067379
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Silicide gate transistors and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/753632
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 8041
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067379.pdf
[firstpage_image] =>[orig_patent_app_number] => 10753632
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/753632 | Silicide gate transistors and method of manufacture | Jan 7, 2004 | Issued |
Array
(
[id] => 7072676
[patent_doc_number] => 20050145942
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'METHOD OF MAKING FIELD EFFECT TRANSISTORS HAVING SELF-ALIGNED SOURCE AND DRAIN REGIONS USING INDEPENDENTLY CONTROLLED SPACER WIDTHS'
[patent_app_type] => utility
[patent_app_number] => 10/707725
[patent_app_country] => US
[patent_app_date] => 2004-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3295
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20050145942.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707725
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707725 | Method of making field effect transistors having self-aligned source and drain regions using independently controlled spacer widths | Jan 6, 2004 | Issued |
Array
(
[id] => 7203782
[patent_doc_number] => 20040087093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Semiconductor device manufacturing method'
[patent_app_type] => new
[patent_app_number] => 10/466311
[patent_app_country] => US
[patent_app_date] => 2003-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7130
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20040087093.pdf
[firstpage_image] =>[orig_patent_app_number] => 10466311
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/466311 | Semiconductor device manufacturing method | Dec 29, 2003 | Issued |
Array
(
[id] => 658095
[patent_doc_number] => 07105390
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Nonplanar transistors with metal gate electrodes'
[patent_app_type] => utility
[patent_app_number] => 10/750061
[patent_app_country] => US
[patent_app_date] => 2003-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 33
[patent_no_of_words] => 16426
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/105/07105390.pdf
[firstpage_image] =>[orig_patent_app_number] => 10750061
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/750061 | Nonplanar transistors with metal gate electrodes | Dec 29, 2003 | Issued |
Array
(
[id] => 899893
[patent_doc_number] => 07338867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-04
[patent_title] => 'Semiconductor device having contact pads and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/747925
[patent_app_country] => US
[patent_app_date] => 2003-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 23
[patent_no_of_words] => 8203
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/338/07338867.pdf
[firstpage_image] =>[orig_patent_app_number] => 10747925
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/747925 | Semiconductor device having contact pads and method for manufacturing the same | Dec 29, 2003 | Issued |
Array
(
[id] => 626991
[patent_doc_number] => 07135374
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-14
[patent_title] => 'MOS transistor and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/746381
[patent_app_country] => US
[patent_app_date] => 2003-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2298
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/135/07135374.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746381
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746381 | MOS transistor and fabrication method thereof | Dec 25, 2003 | Issued |
Array
(
[id] => 769032
[patent_doc_number] => 07005336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Process for forming CMOS transistors and MOS transistors of the drain extension type, with a low gate region resistance, in the same semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 10/746881
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2556
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/005/07005336.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746881
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746881 | Process for forming CMOS transistors and MOS transistors of the drain extension type, with a low gate region resistance, in the same semiconductor substrate | Dec 22, 2003 | Issued |
Array
(
[id] => 985449
[patent_doc_number] => 06924177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-02
[patent_title] => 'Method for producing a thyristor'
[patent_app_type] => utility
[patent_app_number] => 10/744741
[patent_app_country] => US
[patent_app_date] => 2003-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 3022
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/924/06924177.pdf
[firstpage_image] =>[orig_patent_app_number] => 10744741
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/744741 | Method for producing a thyristor | Dec 21, 2003 | Issued |
Array
(
[id] => 749717
[patent_doc_number] => 07022594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-04
[patent_title] => 'Manufacturing method which prevents abnormal gate oxidation'
[patent_app_type] => utility
[patent_app_number] => 10/737821
[patent_app_country] => US
[patent_app_date] => 2003-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 25
[patent_no_of_words] => 6013
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/022/07022594.pdf
[firstpage_image] =>[orig_patent_app_number] => 10737821
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/737821 | Manufacturing method which prevents abnormal gate oxidation | Dec 17, 2003 | Issued |
Array
(
[id] => 694797
[patent_doc_number] => 07071065
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-04
[patent_title] => 'Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/738716
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4022
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/071/07071065.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738716
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738716 | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication | Dec 16, 2003 | Issued |
Array
(
[id] => 1018653
[patent_doc_number] => 06891233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-10
[patent_title] => 'Methods to form dual metal gates by incorporating metals and their conductive oxides'
[patent_app_type] => utility
[patent_app_number] => 10/736942
[patent_app_country] => US
[patent_app_date] => 2003-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3673
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/891/06891233.pdf
[firstpage_image] =>[orig_patent_app_number] => 10736942
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/736942 | Methods to form dual metal gates by incorporating metals and their conductive oxides | Dec 15, 2003 | Issued |
Array
(
[id] => 707731
[patent_doc_number] => 07060616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/731481
[patent_app_country] => US
[patent_app_date] => 2003-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2624
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/060/07060616.pdf
[firstpage_image] =>[orig_patent_app_number] => 10731481
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/731481 | Method of manufacturing semiconductor device | Dec 9, 2003 | Issued |
Array
(
[id] => 1031046
[patent_doc_number] => 06878598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-12
[patent_title] => 'Method of forming thick metal silicide layer on gate electrode'
[patent_app_type] => utility
[patent_app_number] => 10/731761
[patent_app_country] => US
[patent_app_date] => 2003-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5898
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/878/06878598.pdf
[firstpage_image] =>[orig_patent_app_number] => 10731761
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/731761 | Method of forming thick metal silicide layer on gate electrode | Dec 8, 2003 | Issued |
Array
(
[id] => 7178710
[patent_doc_number] => 20050124101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'OXIDE/NITRIDE STACKED IN FINFET SPACER PROCESS'
[patent_app_type] => utility
[patent_app_number] => 10/730582
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5516
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20050124101.pdf
[firstpage_image] =>[orig_patent_app_number] => 10730582
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730582 | Oxide/nitride stacked in FinFET spacer process | Dec 7, 2003 | Issued |