Mary Ann Calabrese

Array ( [id] => 7235260 [patent_doc_number] => 20050079696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Encapsulated MOS transistor gate structures and methods for making the same' [patent_app_type] => utility [patent_app_number] => 10/686011 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4569 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20050079696.pdf [firstpage_image] =>[orig_patent_app_number] => 10686011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7235075 [patent_doc_number] => 20050079674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Multi-level gate SONOS flash memory device with high voltage oxide and method for the fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/683052 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20050079674.pdf [firstpage_image] =>[orig_patent_app_number] => 10683052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7471403 [patent_doc_number] => 20040121529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method of forming a buffer dielectric layer in a semiconductor device and a method of manufacturing a thin film transistor using the same' [patent_app_type] => new [patent_app_number] => 10/679021 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3579 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121529.pdf [firstpage_image] =>[orig_patent_app_number] => 10679021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 982321 [patent_doc_number] => 06927165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method and apparatus for processing substrates and method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/674345 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7524 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927165.pdf [firstpage_image] =>[orig_patent_app_number] => 10674345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700190 [patent_doc_number] => 07067880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Transistor gate structure' [patent_app_type] => utility [patent_app_number] => 10/673362 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 5718 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067880.pdf [firstpage_image] =>[orig_patent_app_number] => 10673362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7116730 [patent_doc_number] => 20050070031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/673262 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070031.pdf [firstpage_image] =>[orig_patent_app_number] => 10673262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 620087 [patent_doc_number] => 07141502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/673597 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2302 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141502.pdf [firstpage_image] =>[orig_patent_app_number] => 10673597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7116764 [patent_doc_number] => 20050070065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Deep trench structure manufacturing process' [patent_app_type] => utility [patent_app_number] => 10/671461 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1492 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070065.pdf [firstpage_image] =>[orig_patent_app_number] => 10671461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7025690 [patent_doc_number] => 20050020084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Method of preparing a surface of a semiconductor wafer to make it epiready' [patent_app_type] => utility [patent_app_number] => 10/671812 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20050020084.pdf [firstpage_image] =>[orig_patent_app_number] => 10671812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7280912 [patent_doc_number] => 20040063289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Reduction in source-drain resistance of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/668211 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5012 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063289.pdf [firstpage_image] =>[orig_patent_app_number] => 10668211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1073682 [patent_doc_number] => 06838347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Method for reducing line edge roughness of oxide material using chemical oxide removal' [patent_app_type] => utility [patent_app_number] => 10/605331 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2620 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838347.pdf [firstpage_image] =>[orig_patent_app_number] => 10605331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7304941 [patent_doc_number] => 20040115902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Semiconductor device, method of manufacturing the same, circuit board, and electronic equipment' [patent_app_type] => new [patent_app_number] => 10/667331 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115902.pdf [firstpage_image] =>[orig_patent_app_number] => 10667331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7010991 [patent_doc_number] => 20050064707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias' [patent_app_type] => utility [patent_app_number] => 10/668914 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7155 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064707.pdf [firstpage_image] =>[orig_patent_app_number] => 10668914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 654585 [patent_doc_number] => 07109104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Methods of fabricating a semiconductor device having a metal gate pattern' [patent_app_type] => utility [patent_app_number] => 10/665122 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6307 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109104.pdf [firstpage_image] =>[orig_patent_app_number] => 10665122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7127472 [patent_doc_number] => 20050059216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER' [patent_app_type] => utility [patent_app_number] => 10/664211 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1579 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20050059216.pdf [firstpage_image] =>[orig_patent_app_number] => 10664211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7605451 [patent_doc_number] => 07115478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method of fabricating a semiconductor device and a method of generating a mask pattern' [patent_app_type] => utility [patent_app_number] => 10/663642 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 9289 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115478.pdf [firstpage_image] =>[orig_patent_app_number] => 10663642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7280911 [patent_doc_number] => 20040063288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'System and method for reducing soft error rate utilizing customized epitaxial layers' [patent_app_type] => new [patent_app_number] => 10/664091 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063288.pdf [firstpage_image] =>[orig_patent_app_number] => 10664091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1085652 [patent_doc_number] => 06830997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Semiconductor devices and methods for forming semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 10/663412 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1263 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/830/06830997.pdf [firstpage_image] =>[orig_patent_app_number] => 10663412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1105007 [patent_doc_number] => 06812149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method of forming junction isolation to isolate active elements' [patent_app_type] => B1 [patent_app_number] => 10/662381 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1339 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812149.pdf [firstpage_image] =>[orig_patent_app_number] => 10662381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1043704 [patent_doc_number] => 06867137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Fabrication method for a semiconductor structure having a partly filled trench' [patent_app_type] => utility [patent_app_number] => 10/660091 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1540 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867137.pdf [firstpage_image] =>[orig_patent_app_number] => 10660091 [rel_patent_id] =>[rel_patent_doc_number] =>)