
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5976934
[patent_doc_number] => 20110070686
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-24
[patent_title] => 'THERMAL MANAGEMENT AND METHOD FOR LARGE SCALE PROCESSING OF CIS AND/OR CIGS BASED THIN FILMS OVERLYING GLASS SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 12/953708
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20110070686.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953708
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953708 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 4492617
[patent_doc_number] => 07955891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-07
[patent_title] => 'Thermal management and method for large scale processing of CIS and /or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953697
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/955/07955891.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953697
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953697 | Thermal management and method for large scale processing of CIS and /or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 4608699
[patent_doc_number] => 07993954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953674
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/993/07993954.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953674
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953674 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 7977349
[patent_doc_number] => 08071421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953701
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/071/08071421.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953701
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953701 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 4608700
[patent_doc_number] => 07993955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953679
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/993/07993955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953679
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953679 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 7555362
[patent_doc_number] => 08067263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-29
[patent_title] => 'Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates'
[patent_app_type] => utility
[patent_app_number] => 12/953716
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 6538
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/067/08067263.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953716
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953716 | Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass substrates | Nov 23, 2010 | Issued |
Array
(
[id] => 8017131
[patent_doc_number] => 08138068
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-20
[patent_title] => 'Method to form nanopore array'
[patent_app_type] => utility
[patent_app_number] => 12/854192
[patent_app_country] => US
[patent_app_date] => 2010-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 30
[patent_no_of_words] => 7823
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/138/08138068.pdf
[firstpage_image] =>[orig_patent_app_number] => 12854192
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/854192 | Method to form nanopore array | Aug 10, 2010 | Issued |
Array
(
[id] => 7777572
[patent_doc_number] => 20120040531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-16
[patent_title] => 'METHOD TO FABRICATE THIN METAL VIA INTERCONNECTS ON COPPER WIRES IN MRAM DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/806381
[patent_app_country] => US
[patent_app_date] => 2010-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8612
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20120040531.pdf
[firstpage_image] =>[orig_patent_app_number] => 12806381
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/806381 | Method to fabricate thin metal via interconnects on copper wires in MRAM devices | Aug 10, 2010 | Issued |
Array
(
[id] => 6130619
[patent_doc_number] => 20110006372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-13
[patent_title] => 'FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/834231
[patent_app_country] => US
[patent_app_date] => 2010-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5670
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20110006372.pdf
[firstpage_image] =>[orig_patent_app_number] => 12834231
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/834231 | Formation of standard voltage threshold and low voltage threshold MOSFET devices | Jul 11, 2010 | Issued |
Array
(
[id] => 8292283
[patent_doc_number] => RE043521
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2012-07-17
[patent_title] => 'Method for manufacturing semiconductor device, including multiple heat treatment'
[patent_app_type] => reissue
[patent_app_number] => 12/819339
[patent_app_country] => US
[patent_app_date] => 2010-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 8509
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12819339
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/819339 | Method for manufacturing semiconductor device, including multiple heat treatment | Jun 20, 2010 | Issued |
Array
(
[id] => 5985739
[patent_doc_number] => 20110097846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-28
[patent_title] => 'SEMICONDUCTOR CHIP, WAFER STACK PACKAGE USING THE SAME, AND METHODS OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/817304
[patent_app_country] => US
[patent_app_date] => 2010-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6470
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20110097846.pdf
[firstpage_image] =>[orig_patent_app_number] => 12817304
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/817304 | Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same | Jun 16, 2010 | Issued |
Array
(
[id] => 8005901
[patent_doc_number] => 08084351
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Contact structure of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/776923
[patent_app_country] => US
[patent_app_date] => 2010-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3016
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/084/08084351.pdf
[firstpage_image] =>[orig_patent_app_number] => 12776923
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/776923 | Contact structure of a semiconductor device | May 9, 2010 | Issued |
Array
(
[id] => 8317360
[patent_doc_number] => 08232138
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-31
[patent_title] => 'Circuit board with notched stiffener frame'
[patent_app_type] => utility
[patent_app_number] => 12/759761
[patent_app_country] => US
[patent_app_date] => 2010-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4486
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759761
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/759761 | Circuit board with notched stiffener frame | Apr 13, 2010 | Issued |
Array
(
[id] => 6570007
[patent_doc_number] => 20100273304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-28
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/760152
[patent_app_country] => US
[patent_app_date] => 2010-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3890
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20100273304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12760152
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/760152 | Method of fabricating semiconductor device | Apr 13, 2010 | Issued |
Array
(
[id] => 7486111
[patent_doc_number] => 20110250725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK'
[patent_app_type] => utility
[patent_app_number] => 12/758491
[patent_app_country] => US
[patent_app_date] => 2010-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4091
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20110250725.pdf
[firstpage_image] =>[orig_patent_app_number] => 12758491
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/758491 | Method of fabricating gate electrode using a treated hard mask | Apr 11, 2010 | Issued |
Array
(
[id] => 8214085
[patent_doc_number] => 08193075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-05
[patent_title] => 'Remote hydrogen plasma with ion filter for terminating silicon dangling bonds'
[patent_app_type] => utility
[patent_app_number] => 12/757341
[patent_app_country] => US
[patent_app_date] => 2010-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3974
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/193/08193075.pdf
[firstpage_image] =>[orig_patent_app_number] => 12757341
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/757341 | Remote hydrogen plasma with ion filter for terminating silicon dangling bonds | Apr 8, 2010 | Issued |
Array
(
[id] => 8282842
[patent_doc_number] => 08216945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-10
[patent_title] => 'Wafer planarity control between pattern levels'
[patent_app_type] => utility
[patent_app_number] => 12/757665
[patent_app_country] => US
[patent_app_date] => 2010-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4064
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12757665
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/757665 | Wafer planarity control between pattern levels | Apr 8, 2010 | Issued |
Array
(
[id] => 6512125
[patent_doc_number] => 20100261304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-14
[patent_title] => 'Solution-based process for making inorganic materials'
[patent_app_type] => utility
[patent_app_number] => 12/798755
[patent_app_country] => US
[patent_app_date] => 2010-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 63
[patent_figures_cnt] => 63
[patent_no_of_words] => 37905
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20100261304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12798755
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/798755 | Solution-based process for making inorganic materials | Apr 8, 2010 | Issued |
Array
(
[id] => 7987775
[patent_doc_number] => 08076182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-13
[patent_title] => 'Method of making a semiconductor chip assembly with a post/base heat spreader and a cavity over the post'
[patent_app_type] => utility
[patent_app_number] => 12/714495
[patent_app_country] => US
[patent_app_date] => 2010-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 51
[patent_no_of_words] => 21217
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/076/08076182.pdf
[firstpage_image] =>[orig_patent_app_number] => 12714495
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/714495 | Method of making a semiconductor chip assembly with a post/base heat spreader and a cavity over the post | Feb 27, 2010 | Issued |
Array
(
[id] => 6438827
[patent_doc_number] => 20100144132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-10
[patent_title] => 'METHODS FOR FORMING NANODOTS AND/OR A PATTERNED MATERIAL DURING THE FORMATION OF A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/705704
[patent_app_country] => US
[patent_app_date] => 2010-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 4514
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20100144132.pdf
[firstpage_image] =>[orig_patent_app_number] => 12705704
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/705704 | Methods for forming nanodots and/or a patterned material during the formation of a semiconductor device | Feb 14, 2010 | Issued |