Mary Ann Calabrese

Array ( [id] => 7304927 [patent_doc_number] => 20040115888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => '[METHOD FOR FABRICATING LOCALLY STRAINED CHANNEL ]' [patent_app_type] => new [patent_app_number] => 10/605122 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3053 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115888.pdf [firstpage_image] =>[orig_patent_app_number] => 10605122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1119638 [patent_doc_number] => 06797555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Direct implantation of fluorine into the channel region of a PMOS device' [patent_app_type] => B1 [patent_app_number] => 10/659422 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1303 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797555.pdf [firstpage_image] =>[orig_patent_app_number] => 10659422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7212699 [patent_doc_number] => 20050054161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays' [patent_app_type] => utility [patent_app_number] => 10/659042 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5626 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20050054161.pdf [firstpage_image] =>[orig_patent_app_number] => 10659042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1080479 [patent_doc_number] => 06835637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Multi-layered gate for a CMOS imager' [patent_app_type] => B2 [patent_app_number] => 10/654932 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7614 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835637.pdf [firstpage_image] =>[orig_patent_app_number] => 10654932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7130202 [patent_doc_number] => 20040041231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/655122 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7704 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041231.pdf [firstpage_image] =>[orig_patent_app_number] => 10655122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629839 [patent_doc_number] => 06818517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Methods of depositing two or more layers on a substrate in situ' [patent_app_type] => B1 [patent_app_number] => 10/652851 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4355 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818517.pdf [firstpage_image] =>[orig_patent_app_number] => 10652851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7122509 [patent_doc_number] => 20050014338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Integration method of a semiconductor device having a recessed gate electrode' [patent_app_type] => utility [patent_app_number] => 10/649262 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2455 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20050014338.pdf [firstpage_image] =>[orig_patent_app_number] => 10649262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7365222 [patent_doc_number] => 20040092089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography' [patent_app_type] => new [patent_app_number] => 10/645032 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2750 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092089.pdf [firstpage_image] =>[orig_patent_app_number] => 10645032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1050039 [patent_doc_number] => 06861316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/637212 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 11484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861316.pdf [firstpage_image] =>[orig_patent_app_number] => 10637212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134344 [patent_doc_number] => 06784081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Gate structure forming method of field effect transistor' [patent_app_type] => B1 [patent_app_number] => 10/604628 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3231 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784081.pdf [firstpage_image] =>[orig_patent_app_number] => 10604628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1123381 [patent_doc_number] => 06794256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method for asymmetric spacer formation' [patent_app_type] => B1 [patent_app_number] => 10/633981 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4262 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794256.pdf [firstpage_image] =>[orig_patent_app_number] => 10633981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7154701 [patent_doc_number] => 20050026365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Nonvolatile memory cell with multiple floating gates formed after the select gate' [patent_app_type] => utility [patent_app_number] => 10/631941 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6956 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026365.pdf [firstpage_image] =>[orig_patent_app_number] => 10631941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1146576 [patent_doc_number] => 06774022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method of passivating an oxide surface subjected to a conductive material anneal' [patent_app_type] => B2 [patent_app_number] => 10/629199 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5960 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774022.pdf [firstpage_image] =>[orig_patent_app_number] => 10629199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7154614 [patent_doc_number] => 20050026337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'THYRISTOR-BASED SRAM AND METHOD FOR THE FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 10/628912 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20050026337.pdf [firstpage_image] =>[orig_patent_app_number] => 10628912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1002361 [patent_doc_number] => 06908815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Dual work function semiconductor structure with borderless contact and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/624781 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4353 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908815.pdf [firstpage_image] =>[orig_patent_app_number] => 10624781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7348270 [patent_doc_number] => 20040012055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Semiconductor device having hetero grain stack gate and method of forming the same' [patent_app_type] => new [patent_app_number] => 10/619581 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4703 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012055.pdf [firstpage_image] =>[orig_patent_app_number] => 10619581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1104881 [patent_doc_number] => 06812105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Ultra-thin channel device with raised source and drain and solid source extension doping' [patent_app_type] => B1 [patent_app_number] => 10/604382 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4275 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812105.pdf [firstpage_image] =>[orig_patent_app_number] => 10604382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7122524 [patent_doc_number] => 20050014353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Method to reduce transistor gate to source/drain overlap capacitance by incorporaton of carbon' [patent_app_type] => utility [patent_app_number] => 10/620492 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8233 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20050014353.pdf [firstpage_image] =>[orig_patent_app_number] => 10620492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7348324 [patent_doc_number] => 20040012067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same' [patent_app_type] => new [patent_app_number] => 10/619981 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2816 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012067.pdf [firstpage_image] =>[orig_patent_app_number] => 10619981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1089079 [patent_doc_number] => 06828184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method of manufacturing semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 10/618292 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1774 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/828/06828184.pdf [firstpage_image] =>[orig_patent_app_number] => 10618292 [rel_patent_id] =>[rel_patent_doc_number] =>)