Mary Ann Calabrese

Array ( [id] => 7086600 [patent_doc_number] => 20050006712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'PECVD silicon-rich oxide layer for reduced UV charging' [patent_app_type] => utility [patent_app_number] => 10/617451 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1815 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006712.pdf [firstpage_image] =>[orig_patent_app_number] => 10617451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1104922 [patent_doc_number] => 06812119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Narrow fins by oxidation in double-gate finfet' [patent_app_type] => B1 [patent_app_number] => 10/614052 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812119.pdf [firstpage_image] =>[orig_patent_app_number] => 10614052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7183275 [patent_doc_number] => 20050161754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Photoelectric conversion apparatus and manufacturing method of same' [patent_app_type] => utility [patent_app_number] => 10/516091 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12851 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161754.pdf [firstpage_image] =>[orig_patent_app_number] => 10516091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7222144 [patent_doc_number] => 20040072446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Method for fabricating an ultra shallow junction of a field effect transistor' [patent_app_type] => new [patent_app_number] => 10/612642 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6132 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20040072446.pdf [firstpage_image] =>[orig_patent_app_number] => 10612642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7433510 [patent_doc_number] => 20040002196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'EDMOS device having a lattice type drift region and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/611502 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3529 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20040002196.pdf [firstpage_image] =>[orig_patent_app_number] => 10611502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 899902 [patent_doc_number] => 07338869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/517772 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8498 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/338/07338869.pdf [firstpage_image] =>[orig_patent_app_number] => 10517772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7383395 [patent_doc_number] => 20040082155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method for forming word line of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/603611 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1284 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082155.pdf [firstpage_image] =>[orig_patent_app_number] => 10603611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1123211 [patent_doc_number] => 06794198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'MOCVD selective deposition of c-axis oriented Pb5Ge3O11 thin films on high-k gate oxides' [patent_app_type] => B1 [patent_app_number] => 10/606057 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1737 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794198.pdf [firstpage_image] =>[orig_patent_app_number] => 10606057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629838 [patent_doc_number] => 06818518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for producing low/high voltage threshold transistors in semiconductor processing' [patent_app_type] => B1 [patent_app_number] => 10/602994 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1853 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818518.pdf [firstpage_image] =>[orig_patent_app_number] => 10602994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7429599 [patent_doc_number] => 20040266122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN IMPROVED DISPOSABLE SPACER' [patent_app_type] => new [patent_app_number] => 10/602241 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5186 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266122.pdf [firstpage_image] =>[orig_patent_app_number] => 10602241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1065555 [patent_doc_number] => 06846708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Semiconductor device having improved doping profiles and a method of improving the doping profiles of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/601717 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6977 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/846/06846708.pdf [firstpage_image] =>[orig_patent_app_number] => 10601717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1065577 [patent_doc_number] => 06846720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Method to reduce junction leakage current in strained silicon on silicon-germanium devices' [patent_app_type] => utility [patent_app_number] => 10/464282 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2432 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/846/06846720.pdf [firstpage_image] =>[orig_patent_app_number] => 10464282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1062800 [patent_doc_number] => 06849544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Forming a conductive structure in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/454218 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4068 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849544.pdf [firstpage_image] =>[orig_patent_app_number] => 10454218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7343226 [patent_doc_number] => 20040046192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Process for fabricating a MOS transistor of short gate length and integrated circuit comprising such a transistor' [patent_app_type] => new [patent_app_number] => 10/454361 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3016 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20040046192.pdf [firstpage_image] =>[orig_patent_app_number] => 10454361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6664286 [patent_doc_number] => 20030203612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same' [patent_app_type] => new [patent_app_number] => 10/446384 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9721 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203612.pdf [firstpage_image] =>[orig_patent_app_number] => 10446384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1101715 [patent_doc_number] => 06815320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Method for fabricating semiconductor device including gate spacer' [patent_app_type] => B2 [patent_app_number] => 10/444221 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4322 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815320.pdf [firstpage_image] =>[orig_patent_app_number] => 10444221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7171650 [patent_doc_number] => 20040200500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Ultrasonic-wave washing unit, ultrasonic-wave washing apparatus, ultrasonic-wave washing method, method of manufacturing a semiconductor device, and method of manufacturing a liquid crystal display' [patent_app_type] => new [patent_app_number] => 10/443012 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8929 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20040200500.pdf [firstpage_image] =>[orig_patent_app_number] => 10443012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1115607 [patent_doc_number] => 06800536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Semiconductor device having an insulated gate and a fabrication process thereof' [patent_app_type] => B2 [patent_app_number] => 10/442224 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4306 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800536.pdf [firstpage_image] =>[orig_patent_app_number] => 10442224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7313609 [patent_doc_number] => 20040033658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Method of fabricating MOS transistors' [patent_app_type] => new [patent_app_number] => 10/437881 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2989 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033658.pdf [firstpage_image] =>[orig_patent_app_number] => 10437881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1050026 [patent_doc_number] => 06861303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'JFET structure for integrated circuit and fabrication method' [patent_app_type] => utility [patent_app_number] => 10/434642 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 9761 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861303.pdf [firstpage_image] =>[orig_patent_app_number] => 10434642 [rel_patent_id] =>[rel_patent_doc_number] =>)