Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1192885 [patent_doc_number] => 06730531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method for forming quantum dot' [patent_app_type] => B2 [patent_app_number] => 10/320402 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2730 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730531.pdf [firstpage_image] =>[orig_patent_app_number] => 10320402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/320402
Method for forming quantum dot Dec 16, 2002 Issued
Array ( [id] => 1104781 [patent_doc_number] => 06812069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method for improving semiconductor process wafer CMP uniformity while avoiding fracture' [patent_app_type] => B2 [patent_app_number] => 10/322691 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3807 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812069.pdf [firstpage_image] =>[orig_patent_app_number] => 10322691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322691
Method for improving semiconductor process wafer CMP uniformity while avoiding fracture Dec 16, 2002 Issued
Array ( [id] => 7383392 [patent_doc_number] => 20040082154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'METHOD FOR FABRICATING IMAGE SENSOR USING SALICIDE PROCESS' [patent_app_type] => new [patent_app_number] => 10/318072 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3434 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082154.pdf [firstpage_image] =>[orig_patent_app_number] => 10318072 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318072
Method for fabricating image sensor using salicide process Dec 12, 2002 Issued
Array ( [id] => 1209263 [patent_doc_number] => 06713338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for fabricating source/drain devices' [patent_app_type] => B2 [patent_app_number] => 10/315992 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 2580 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713338.pdf [firstpage_image] =>[orig_patent_app_number] => 10315992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315992
Method for fabricating source/drain devices Dec 10, 2002 Issued
Array ( [id] => 7289756 [patent_doc_number] => 20040110352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'SOURCE DRAIN AND EXTENSION DOPANT CONCENTRATION' [patent_app_type] => new [patent_app_number] => 10/316468 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110352.pdf [firstpage_image] =>[orig_patent_app_number] => 10316468 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316468
Source drain and extension dopant concentration Dec 9, 2002 Issued
Array ( [id] => 1264446 [patent_doc_number] => 06660604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method of forming double junction region and method of forming transfer transistor using the same' [patent_app_type] => B1 [patent_app_number] => 10/314442 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2903 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660604.pdf [firstpage_image] =>[orig_patent_app_number] => 10314442 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314442
Method of forming double junction region and method of forming transfer transistor using the same Dec 8, 2002 Issued
Array ( [id] => 472371 [patent_doc_number] => 07229847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Forming electrical contacts to a molecular layer' [patent_app_type] => utility [patent_app_number] => 10/307642 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5078 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/229/07229847.pdf [firstpage_image] =>[orig_patent_app_number] => 10307642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307642
Forming electrical contacts to a molecular layer Dec 1, 2002 Issued
Array ( [id] => 509322 [patent_doc_number] => 07195931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Split manufacturing method for advanced semiconductor circuits' [patent_app_type] => utility [patent_app_number] => 10/305670 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4475 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/195/07195931.pdf [firstpage_image] =>[orig_patent_app_number] => 10305670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/305670
Split manufacturing method for advanced semiconductor circuits Nov 26, 2002 Issued
Array ( [id] => 6696927 [patent_doc_number] => 20030109121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Multiple work function gates' [patent_app_type] => new [patent_app_number] => 10/302212 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4764 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109121.pdf [firstpage_image] =>[orig_patent_app_number] => 10302212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302212
Multiple work function gates Nov 21, 2002 Issued
Array ( [id] => 7472194 [patent_doc_number] => 20040097071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Method of electoless deposition of thin metal and dielectric films with temperature controlled on stages of film growth' [patent_app_type] => new [patent_app_number] => 10/299070 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9557 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20040097071.pdf [firstpage_image] =>[orig_patent_app_number] => 10299070 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299070
Method of electroless deposition of thin metal and dielectric films with temperature controlled stages of film growth Nov 18, 2002 Issued
Array ( [id] => 1264451 [patent_doc_number] => 06660605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss' [patent_app_type] => B1 [patent_app_number] => 10/292722 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 9556 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660605.pdf [firstpage_image] =>[orig_patent_app_number] => 10292722 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292722
Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss Nov 11, 2002 Issued
Array ( [id] => 1146517 [patent_doc_number] => 06774012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Furnace system and method for selectively oxidizing a sidewall surface of a gate conductor by oxidizing a silicon sidewall in lieu of a refractory metal sidewall' [patent_app_type] => B1 [patent_app_number] => 10/290841 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4766 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774012.pdf [firstpage_image] =>[orig_patent_app_number] => 10290841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290841
Furnace system and method for selectively oxidizing a sidewall surface of a gate conductor by oxidizing a silicon sidewall in lieu of a refractory metal sidewall Nov 7, 2002 Issued
Array ( [id] => 6761463 [patent_doc_number] => 20030124825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Method of forming a gate electrode in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/284472 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2228 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124825.pdf [firstpage_image] =>[orig_patent_app_number] => 10284472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/284472
Method of forming a gate electrode in a semiconductor device Oct 30, 2002 Issued
Array ( [id] => 1221675 [patent_doc_number] => 06703648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication' [patent_app_type] => B1 [patent_app_number] => 10/282559 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3985 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703648.pdf [firstpage_image] =>[orig_patent_app_number] => 10282559 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282559
Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication Oct 28, 2002 Issued
Array ( [id] => 1196628 [patent_doc_number] => 06727136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Formation of ultra-shallow depth source/drain extensions for MOS transistors' [patent_app_type] => B1 [patent_app_number] => 10/273291 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 4822 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727136.pdf [firstpage_image] =>[orig_patent_app_number] => 10273291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273291
Formation of ultra-shallow depth source/drain extensions for MOS transistors Oct 17, 2002 Issued
Array ( [id] => 1297476 [patent_doc_number] => 06627527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method to reduce metal silicide void formation' [patent_app_type] => B1 [patent_app_number] => 10/268212 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2512 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627527.pdf [firstpage_image] =>[orig_patent_app_number] => 10268212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268212
Method to reduce metal silicide void formation Oct 9, 2002 Issued
Array ( [id] => 7433883 [patent_doc_number] => 20040065936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Transistor structures including separate anti-punchthrough layers and methods of forming same' [patent_app_type] => new [patent_app_number] => 10/266811 [patent_app_country] => US [patent_app_date] => 2002-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3584 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20040065936.pdf [firstpage_image] =>[orig_patent_app_number] => 10266811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/266811
Methods of forming transistor structures including separate anti-punchthrough layers Oct 7, 2002 Issued
Array ( [id] => 1276802 [patent_doc_number] => 06649966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Quantum dot of single electron memory device and method for fabricating thereof' [patent_app_type] => B2 [patent_app_number] => 10/265320 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649966.pdf [firstpage_image] =>[orig_patent_app_number] => 10265320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/265320
Quantum dot of single electron memory device and method for fabricating thereof Oct 6, 2002 Issued
Array ( [id] => 1090618 [patent_doc_number] => 06824319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Tripod particularly for optical and photographic use' [patent_app_type] => B1 [patent_app_number] => 10/148729 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1593 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/824/06824319.pdf [firstpage_image] =>[orig_patent_app_number] => 10148729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/148729
Tripod particularly for optical and photographic use Oct 2, 2002 Issued
Array ( [id] => 7607666 [patent_doc_number] => 07098048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Method and apparatus for capturing fault state data' [patent_app_type] => utility [patent_app_number] => 10/261611 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3479 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098048.pdf [firstpage_image] =>[orig_patent_app_number] => 10261611 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261611
Method and apparatus for capturing fault state data Sep 29, 2002 Issued
Menu