
Mary Ann Calabrese
Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )
| Most Active Art Unit | 2913 |
| Art Unit(s) | 2931, 2913 |
| Total Applications | 4141 |
| Issued Applications | 3855 |
| Pending Applications | 21 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1306627
[patent_doc_number] => 06617218
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-09
[patent_title] => 'Manufacturing method for semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/192552
[patent_app_country] => US
[patent_app_date] => 2002-07-11
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[pdf_file] => patents/06/617/06617218.pdf
[firstpage_image] =>[orig_patent_app_number] => 10192552
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192552 | Manufacturing method for semiconductor device | Jul 10, 2002 | Issued |
Array
(
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[patent_doc_number] => 20040004260
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[patent_issue_date] => 2004-01-08
[patent_title] => 'METHOD OF FORMING DUAL-IMPLANTED GATE AND STRUCTURE FORMED BY THE SAME'
[patent_app_type] => new
[patent_app_number] => 10/064372
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[pdf_file] => publications/A1/0004/20040004260.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064372 | Method of forming dual-implanted gate and structure formed by the same | Jul 7, 2002 | Issued |
Array
(
[id] => 1248283
[patent_doc_number] => 06673717
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-06
[patent_title] => 'Methods for fabricating nanopores for single-electron devices'
[patent_app_type] => B1
[patent_app_number] => 10/180572
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/180572 | Methods for fabricating nanopores for single-electron devices | Jun 25, 2002 | Issued |
Array
(
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[patent_doc_number] => 06844585
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-18
[patent_title] => 'Circuit and method of forming the circuit having subsurface conductors'
[patent_app_type] => utility
[patent_app_number] => 10/173911
[patent_app_country] => US
[patent_app_date] => 2002-06-17
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/173911 | Circuit and method of forming the circuit having subsurface conductors | Jun 16, 2002 | Issued |
Array
(
[id] => 1009332
[patent_doc_number] => 06900094
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[patent_issue_date] => 2005-05-31
[patent_title] => 'Method of selective removal of SiGe alloys'
[patent_app_type] => utility
[patent_app_number] => 10/172542
[patent_app_country] => US
[patent_app_date] => 2002-06-14
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[firstpage_image] =>[orig_patent_app_number] => 10172542
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172542 | Method of selective removal of SiGe alloys | Jun 13, 2002 | Issued |
Array
(
[id] => 6678573
[patent_doc_number] => 20030228714
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[patent_issue_date] => 2003-12-11
[patent_title] => 'Dummy fill for integrated circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/165214 | Dummy fill for integrated circuits | Jun 6, 2002 | Issued |
Array
(
[id] => 1310591
[patent_doc_number] => 06613637
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Composite spacer scheme with low overlapped parasitic capacitance'
[patent_app_type] => B1
[patent_app_number] => 10/160812
[patent_app_country] => US
[patent_app_date] => 2002-05-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10160812
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/160812 | Composite spacer scheme with low overlapped parasitic capacitance | May 30, 2002 | Issued |
Array
(
[id] => 6801325
[patent_doc_number] => 20030096490
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Method of forming ultra shallow junctions'
[patent_app_type] => new
[patent_app_number] => 10/156981
[patent_app_country] => US
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[pdf_file] => publications/A1/0096/20030096490.pdf
[firstpage_image] =>[orig_patent_app_number] => 10156981
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/156981 | Method of forming ultra shallow junctions | May 28, 2002 | Abandoned |
Array
(
[id] => 946560
[patent_doc_number] => 06964892
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/155731 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | May 27, 2002 | Issued |
Array
(
[id] => 6821827
[patent_doc_number] => 20030219988
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[patent_issue_date] => 2003-11-27
[patent_title] => 'Ashable layers for reducing critical dimensions of integrated circuit features'
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[patent_app_number] => 10/154532
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/154532 | Ashable layers for reducing critical dimensions of integrated circuit features | May 21, 2002 | Issued |
Array
(
[id] => 6530462
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[patent_title] => 'Method for fabricating semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/152341 | Method for fabricating semiconductor device | May 21, 2002 | Issued |
Array
(
[id] => 6669003
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[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE'
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[firstpage_image] =>[orig_patent_app_number] => 10141922
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/141922 | Method of manufacturing a semiconductor device | May 9, 2002 | Issued |
Array
(
[id] => 1288735
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[patent_title] => 'Transistor of semiconductor device and method of manufacturing the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/141171 | Transistor of semiconductor device and method of manufacturing the same | May 8, 2002 | Issued |
Array
(
[id] => 6725230
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[patent_title] => 'FABRICATION OF ABRUPT ULTRA-SHALLOW JUNCTIONS USING ANGLED PAI AND FLUORINE IMPLANT'
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[firstpage_image] =>[orig_patent_app_number] => 10139672
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/139672 | Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant | May 5, 2002 | Issued |
Array
(
[id] => 724407
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[patent_title] => 'Atomic layer-deposited LaAlO3 films for gate dielectrics'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137499 | Atomic layer-deposited LaAlO3 films for gate dielectrics | May 1, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/136324 | Structure and method for fabricating an integrated phased array circuit | May 1, 2002 | Abandoned |
Array
(
[id] => 1359858
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[patent_title] => 'Silicon carbide semiconductor device and manufacturing method'
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Array
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Array
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Array
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