Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1306627 [patent_doc_number] => 06617218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Manufacturing method for semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/192552 [patent_app_country] => US [patent_app_date] => 2002-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3532 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617218.pdf [firstpage_image] =>[orig_patent_app_number] => 10192552 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192552
Manufacturing method for semiconductor device Jul 10, 2002 Issued
Array ( [id] => 7357081 [patent_doc_number] => 20040004260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'METHOD OF FORMING DUAL-IMPLANTED GATE AND STRUCTURE FORMED BY THE SAME' [patent_app_type] => new [patent_app_number] => 10/064372 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004260.pdf [firstpage_image] =>[orig_patent_app_number] => 10064372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064372
Method of forming dual-implanted gate and structure formed by the same Jul 7, 2002 Issued
Array ( [id] => 1248283 [patent_doc_number] => 06673717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Methods for fabricating nanopores for single-electron devices' [patent_app_type] => B1 [patent_app_number] => 10/180572 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 5399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673717.pdf [firstpage_image] =>[orig_patent_app_number] => 10180572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180572
Methods for fabricating nanopores for single-electron devices Jun 25, 2002 Issued
Array ( [id] => 1069162 [patent_doc_number] => 06844585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Circuit and method of forming the circuit having subsurface conductors' [patent_app_type] => utility [patent_app_number] => 10/173911 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 4098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844585.pdf [firstpage_image] =>[orig_patent_app_number] => 10173911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173911
Circuit and method of forming the circuit having subsurface conductors Jun 16, 2002 Issued
Array ( [id] => 1009332 [patent_doc_number] => 06900094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method of selective removal of SiGe alloys' [patent_app_type] => utility [patent_app_number] => 10/172542 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2543 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900094.pdf [firstpage_image] =>[orig_patent_app_number] => 10172542 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172542
Method of selective removal of SiGe alloys Jun 13, 2002 Issued
Array ( [id] => 6678573 [patent_doc_number] => 20030228714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Dummy fill for integrated circuits' [patent_app_type] => new [patent_app_number] => 10/165214 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 16913 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20030228714.pdf [firstpage_image] =>[orig_patent_app_number] => 10165214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/165214
Dummy fill for integrated circuits Jun 6, 2002 Issued
Array ( [id] => 1310591 [patent_doc_number] => 06613637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Composite spacer scheme with low overlapped parasitic capacitance' [patent_app_type] => B1 [patent_app_number] => 10/160812 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3579 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613637.pdf [firstpage_image] =>[orig_patent_app_number] => 10160812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/160812
Composite spacer scheme with low overlapped parasitic capacitance May 30, 2002 Issued
Array ( [id] => 6801325 [patent_doc_number] => 20030096490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method of forming ultra shallow junctions' [patent_app_type] => new [patent_app_number] => 10/156981 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2931 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096490.pdf [firstpage_image] =>[orig_patent_app_number] => 10156981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/156981
Method of forming ultra shallow junctions May 28, 2002 Abandoned
Array ( [id] => 946560 [patent_doc_number] => 06964892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same' [patent_app_type] => utility [patent_app_number] => 10/155731 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4856 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964892.pdf [firstpage_image] =>[orig_patent_app_number] => 10155731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155731
N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same May 27, 2002 Issued
Array ( [id] => 6821827 [patent_doc_number] => 20030219988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Ashable layers for reducing critical dimensions of integrated circuit features' [patent_app_type] => new [patent_app_number] => 10/154532 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3503 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20030219988.pdf [firstpage_image] =>[orig_patent_app_number] => 10154532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154532
Ashable layers for reducing critical dimensions of integrated circuit features May 21, 2002 Issued
Array ( [id] => 6530462 [patent_doc_number] => 20020192915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/152341 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5439 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192915.pdf [firstpage_image] =>[orig_patent_app_number] => 10152341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152341
Method for fabricating semiconductor device May 21, 2002 Issued
Array ( [id] => 6669003 [patent_doc_number] => 20030113987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/141922 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2842 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113987.pdf [firstpage_image] =>[orig_patent_app_number] => 10141922 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/141922
Method of manufacturing a semiconductor device May 9, 2002 Issued
Array ( [id] => 1288735 [patent_doc_number] => 06632717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Transistor of semiconductor device and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/141171 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 1989 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632717.pdf [firstpage_image] =>[orig_patent_app_number] => 10141171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/141171
Transistor of semiconductor device and method of manufacturing the same May 8, 2002 Issued
Array ( [id] => 6725230 [patent_doc_number] => 20030207542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'FABRICATION OF ABRUPT ULTRA-SHALLOW JUNCTIONS USING ANGLED PAI AND FLUORINE IMPLANT' [patent_app_type] => new [patent_app_number] => 10/139672 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4540 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207542.pdf [firstpage_image] =>[orig_patent_app_number] => 10139672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139672
Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant May 5, 2002 Issued
Array ( [id] => 724407 [patent_doc_number] => 07045430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Atomic layer-deposited LaAlO3 films for gate dielectrics' [patent_app_type] => utility [patent_app_number] => 10/137499 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10538 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045430.pdf [firstpage_image] =>[orig_patent_app_number] => 10137499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137499
Atomic layer-deposited LaAlO3 films for gate dielectrics May 1, 2002 Issued
Array ( [id] => 6745212 [patent_doc_number] => 20030022395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Structure and method for fabricating an integrated phased array circuit' [patent_app_type] => new [patent_app_number] => 10/136324 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 25616 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022395.pdf [firstpage_image] =>[orig_patent_app_number] => 10136324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136324
Structure and method for fabricating an integrated phased array circuit May 1, 2002 Abandoned
Array ( [id] => 1359858 [patent_doc_number] => 06576929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Silicon carbide semiconductor device and manufacturing method' [patent_app_type] => B2 [patent_app_number] => 10/135522 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 62 [patent_no_of_words] => 10738 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576929.pdf [firstpage_image] =>[orig_patent_app_number] => 10135522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135522
Silicon carbide semiconductor device and manufacturing method Apr 30, 2002 Issued
Array ( [id] => 1177129 [patent_doc_number] => 06743666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Selective thickening of the source-drain and gate areas of field effect transistors' [patent_app_type] => B1 [patent_app_number] => 10/134981 [patent_app_country] => US [patent_app_date] => 2002-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3146 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743666.pdf [firstpage_image] =>[orig_patent_app_number] => 10134981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/134981
Selective thickening of the source-drain and gate areas of field effect transistors Apr 28, 2002 Issued
Array ( [id] => 1310230 [patent_doc_number] => 06613592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'IMD oxide crack monitor pattern and design rule' [patent_app_type] => B1 [patent_app_number] => 10/132358 [patent_app_country] => US [patent_app_date] => 2002-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613592.pdf [firstpage_image] =>[orig_patent_app_number] => 10132358 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/132358
IMD oxide crack monitor pattern and design rule Apr 24, 2002 Issued
Array ( [id] => 6327329 [patent_doc_number] => 20020197805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method for fabricating a MOS transistor using a self-aligned silicide technique' [patent_app_type] => new [patent_app_number] => 10/131418 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3015 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20020197805.pdf [firstpage_image] =>[orig_patent_app_number] => 10131418 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/131418
Method for fabricating a MOS transistor using a self-aligned silicide technique Apr 21, 2002 Issued
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