Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6170159 [patent_doc_number] => 20020153562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/125271 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2438 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20020153562.pdf [firstpage_image] =>[orig_patent_app_number] => 10125271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125271
Method for fabricating semiconductor device Apr 17, 2002 Issued
Array ( [id] => 1379099 [patent_doc_number] => 06555445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/121542 [patent_app_country] => US [patent_app_date] => 2002-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4876 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555445.pdf [firstpage_image] =>[orig_patent_app_number] => 10121542 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/121542
Manufacturing method of semiconductor device Apr 11, 2002 Issued
Array ( [id] => 1285215 [patent_doc_number] => 06638841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method for reducing gate length bias' [patent_app_type] => B2 [patent_app_number] => 10/117042 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638841.pdf [firstpage_image] =>[orig_patent_app_number] => 10117042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117042
Method for reducing gate length bias Apr 7, 2002 Issued
Array ( [id] => 6801319 [patent_doc_number] => 20030096484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method of fabricating MOS transistor having shallow source/drain junction regions' [patent_app_type] => new [patent_app_number] => 10/117001 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7198 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096484.pdf [firstpage_image] =>[orig_patent_app_number] => 10117001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117001
Method of fabricating MOS transistor having shallow source/drain junction regions Apr 4, 2002 Issued
Array ( [id] => 1416640 [patent_doc_number] => 06509252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/114452 [patent_app_country] => US [patent_app_date] => 2002-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 4763 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509252.pdf [firstpage_image] =>[orig_patent_app_number] => 10114452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/114452
Method of manufacturing semiconductor device Apr 2, 2002 Issued
Array ( [id] => 1303012 [patent_doc_number] => 06620715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method for forming sub-critical dimension structures in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 10/112782 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 9278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620715.pdf [firstpage_image] =>[orig_patent_app_number] => 10112782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/112782
Method for forming sub-critical dimension structures in an integrated circuit Mar 28, 2002 Issued
Array ( [id] => 1419539 [patent_doc_number] => 06525408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same' [patent_app_type] => B2 [patent_app_number] => 10/107969 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9615 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525408.pdf [firstpage_image] =>[orig_patent_app_number] => 10107969 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/107969
Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same Mar 26, 2002 Issued
Array ( [id] => 5906803 [patent_doc_number] => 20020142556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Method for manufacturing transistor of double spacer structure' [patent_app_type] => new [patent_app_number] => 10/103692 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2022 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20020142556.pdf [firstpage_image] =>[orig_patent_app_number] => 10103692 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103692
Method for manufacturing transistor of double spacer structure Mar 24, 2002 Issued
Array ( [id] => 1220546 [patent_doc_number] => 06703297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method of removing inorganic gate antireflective coating after spacer formation' [patent_app_type] => B1 [patent_app_number] => 10/104461 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703297.pdf [firstpage_image] =>[orig_patent_app_number] => 10104461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/104461
Method of removing inorganic gate antireflective coating after spacer formation Mar 21, 2002 Issued
Array ( [id] => 6306732 [patent_doc_number] => 20020094647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/100595 [patent_app_country] => US [patent_app_date] => 2002-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6912 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094647.pdf [firstpage_image] =>[orig_patent_app_number] => 10100595 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100595
Method of manufacturing a semiconductor device Mar 17, 2002 Issued
Array ( [id] => 1367604 [patent_doc_number] => 06566245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method of manufacturing probe unit and probe unit manufactured using this method' [patent_app_type] => B2 [patent_app_number] => 10/090828 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566245.pdf [firstpage_image] =>[orig_patent_app_number] => 10090828 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/090828
Method of manufacturing probe unit and probe unit manufactured using this method Mar 5, 2002 Issued
Array ( [id] => 7203945 [patent_doc_number] => 20050042838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Fluxless assembly of chip size semiconductor packages' [patent_app_type] => utility [patent_app_number] => 10/501431 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20050042838.pdf [firstpage_image] =>[orig_patent_app_number] => 10501431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/501431
Fluxless assembly of chip size semiconductor packages Feb 28, 2002 Issued
Array ( [id] => 1409335 [patent_doc_number] => 06528373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Layered dielectric on silicon carbide semiconductor structures' [patent_app_type] => B2 [patent_app_number] => 10/083071 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6708 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528373.pdf [firstpage_image] =>[orig_patent_app_number] => 10083071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083071
Layered dielectric on silicon carbide semiconductor structures Feb 25, 2002 Issued
Array ( [id] => 6834809 [patent_doc_number] => 20030162355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'POWER SIC DEVICES HAVING RAISED GUARD RINGS' [patent_app_type] => new [patent_app_number] => 10/079892 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3997 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20030162355.pdf [firstpage_image] =>[orig_patent_app_number] => 10079892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079892
Power SiC devices having raised guard rings Feb 21, 2002 Issued
Array ( [id] => 1412482 [patent_doc_number] => 06524938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method for gate formation with improved spacer profile control' [patent_app_type] => B1 [patent_app_number] => 10/075842 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5545 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524938.pdf [firstpage_image] =>[orig_patent_app_number] => 10075842 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075842
Method for gate formation with improved spacer profile control Feb 12, 2002 Issued
Array ( [id] => 6176777 [patent_doc_number] => 20020155689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Highly reliable gate oxide and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/068836 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4947 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155689.pdf [firstpage_image] =>[orig_patent_app_number] => 10068836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068836
Highly reliable gate oxide and method of fabrication Feb 10, 2002 Issued
Array ( [id] => 6269720 [patent_doc_number] => 20020105080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Method of forming an electronic device' [patent_app_type] => new [patent_app_number] => 10/068453 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 25327 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105080.pdf [firstpage_image] =>[orig_patent_app_number] => 10068453 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068453
Method of forming an electronic device Feb 5, 2002 Issued
Array ( [id] => 7601450 [patent_doc_number] => 07385254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Structure for protection against radio disturbances' [patent_app_type] => utility [patent_app_number] => 10/467194 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1742 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/385/07385254.pdf [firstpage_image] =>[orig_patent_app_number] => 10467194 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/467194
Structure for protection against radio disturbances Feb 3, 2002 Issued
Array ( [id] => 1367066 [patent_doc_number] => 06566205 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method to neutralize fixed charges in high K dielectric' [patent_app_type] => B1 [patent_app_number] => 10/043481 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1337 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566205.pdf [firstpage_image] =>[orig_patent_app_number] => 10043481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043481
Method to neutralize fixed charges in high K dielectric Jan 10, 2002 Issued
Array ( [id] => 1371931 [patent_doc_number] => 06562707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method of forming a semiconductor device using selective epitaxial growth' [patent_app_type] => B2 [patent_app_number] => 10/043942 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2229 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562707.pdf [firstpage_image] =>[orig_patent_app_number] => 10043942 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043942
Method of forming a semiconductor device using selective epitaxial growth Jan 9, 2002 Issued
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