Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1354450 [patent_doc_number] => 06576516 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon' [patent_app_type] => B1 [patent_app_number] => 10/039241 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3619 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576516.pdf [firstpage_image] =>[orig_patent_app_number] => 10039241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039241
High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon Dec 30, 2001 Issued
Array ( [id] => 1279253 [patent_doc_number] => 06650381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Base of architecture of LCD backlight shield' [patent_app_type] => B2 [patent_app_number] => 10/028828 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1004 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/650/06650381.pdf [firstpage_image] =>[orig_patent_app_number] => 10028828 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028828
Base of architecture of LCD backlight shield Dec 27, 2001 Issued
Array ( [id] => 1378557 [patent_doc_number] => 06555411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Thin film transistors' [patent_app_type] => B1 [patent_app_number] => 10/024831 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555411.pdf [firstpage_image] =>[orig_patent_app_number] => 10024831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/024831
Thin film transistors Dec 17, 2001 Issued
Array ( [id] => 5782814 [patent_doc_number] => 20020158289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Method for fabricating SRAM cell' [patent_app_type] => new [patent_app_number] => 10/012491 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3366 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158289.pdf [firstpage_image] =>[orig_patent_app_number] => 10012491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/012491
Method for fabricating SRAM cell Dec 11, 2001 Issued
Array ( [id] => 1588823 [patent_doc_number] => 06482706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method to scale down device dimension using spacer to confine buried drain implant' [patent_app_type] => B1 [patent_app_number] => 10/013982 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482706.pdf [firstpage_image] =>[orig_patent_app_number] => 10013982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013982
Method to scale down device dimension using spacer to confine buried drain implant Dec 9, 2001 Issued
Array ( [id] => 5826907 [patent_doc_number] => 20020067454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Liquid crystal display device of reflective type fringe field switching mode' [patent_app_type] => new [patent_app_number] => 10/004626 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4415 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067454.pdf [firstpage_image] =>[orig_patent_app_number] => 10004626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004626
Liquid crystal display device of reflective type fringe field switching mode Dec 3, 2001 Issued
Array ( [id] => 1588946 [patent_doc_number] => 06482738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method of locally forming metal silicide layers' [patent_app_type] => B1 [patent_app_number] => 09/996821 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2184 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482738.pdf [firstpage_image] =>[orig_patent_app_number] => 09996821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996821
Method of locally forming metal silicide layers Nov 29, 2001 Issued
Array ( [id] => 1346332 [patent_doc_number] => 06583029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Production method for silicon wafer and SOI wafer, and SOI wafer' [patent_app_type] => B2 [patent_app_number] => 09/926645 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8090 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583029.pdf [firstpage_image] =>[orig_patent_app_number] => 09926645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/926645
Production method for silicon wafer and SOI wafer, and SOI wafer Nov 27, 2001 Issued
Array ( [id] => 1315455 [patent_doc_number] => 06607959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'Integrated circuit devices having trench isolation structures and methods of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 09/995351 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4213 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607959.pdf [firstpage_image] =>[orig_patent_app_number] => 09995351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995351
Integrated circuit devices having trench isolation structures and methods of fabricating the same Nov 26, 2001 Issued
Array ( [id] => 7462600 [patent_doc_number] => 20040198030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Vapor phase etch trim structure with top etch blocking layer' [patent_app_type] => new [patent_app_number] => 09/989822 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5182 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198030.pdf [firstpage_image] =>[orig_patent_app_number] => 09989822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989822
Vapor phase etch trim structure with top etch blocking layer Nov 19, 2001 Issued
Array ( [id] => 7375885 [patent_doc_number] => 20040219769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Method and structure for improving latch-up immunity using non-dopant implants' [patent_app_type] => new [patent_app_number] => 09/991771 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4134 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219769.pdf [firstpage_image] =>[orig_patent_app_number] => 09991771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991771
Method and structure for improving latch-up immunity using non-dopant implants Nov 15, 2001 Issued
Array ( [id] => 1419123 [patent_doc_number] => 06506651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/986581 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 7655 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506651.pdf [firstpage_image] =>[orig_patent_app_number] => 09986581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986581
Semiconductor device and manufacturing method thereof Nov 8, 2001 Issued
Array ( [id] => 1440044 [patent_doc_number] => 06495422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application' [patent_app_type] => B1 [patent_app_number] => 10/035552 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1813 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495422.pdf [firstpage_image] =>[orig_patent_app_number] => 10035552 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035552
Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application Nov 8, 2001 Issued
Array ( [id] => 1410698 [patent_doc_number] => 06534857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Thermally balanced power transistor' [patent_app_type] => B1 [patent_app_number] => 09/985402 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2439 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534857.pdf [firstpage_image] =>[orig_patent_app_number] => 09985402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/985402
Thermally balanced power transistor Nov 1, 2001 Issued
Array ( [id] => 1410167 [patent_doc_number] => 06528423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL' [patent_app_type] => B1 [patent_app_number] => 10/002831 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528423.pdf [firstpage_image] =>[orig_patent_app_number] => 10002831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002831
PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL Oct 25, 2001 Issued
Array ( [id] => 6209458 [patent_doc_number] => 20020072253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method of removing an amorphous oxide from a monocrystalline surface' [patent_app_type] => new [patent_app_number] => 09/983854 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3137 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072253.pdf [firstpage_image] =>[orig_patent_app_number] => 09983854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983854
Method of removing an amorphous oxide from a monocrystalline surface Oct 25, 2001 Issued
Array ( [id] => 6870144 [patent_doc_number] => 20030082833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Method for fabricating semiconductor structures utilizing the formation of a compliant substrate' [patent_app_type] => new [patent_app_number] => 09/983869 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9947 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082833.pdf [firstpage_image] =>[orig_patent_app_number] => 09983869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983869
Method for fabricating semiconductor structures utilizing the formation of a compliant substrate Oct 25, 2001 Abandoned
Array ( [id] => 1602608 [patent_doc_number] => 06432787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact' [patent_app_type] => B1 [patent_app_number] => 09/982822 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 3590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432787.pdf [firstpage_image] =>[orig_patent_app_number] => 09982822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/982822
Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact Oct 21, 2001 Issued
Array ( [id] => 1054443 [patent_doc_number] => 06859241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Method of producing polarizing plate, and liquid crystal display comprising the polarizing plate' [patent_app_type] => utility [patent_app_number] => 09/981614 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6199 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859241.pdf [firstpage_image] =>[orig_patent_app_number] => 09981614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981614
Method of producing polarizing plate, and liquid crystal display comprising the polarizing plate Oct 15, 2001 Issued
Array ( [id] => 1286964 [patent_doc_number] => 06642975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Transfer apparatus' [patent_app_type] => B2 [patent_app_number] => 09/973815 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 11228 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642975.pdf [firstpage_image] =>[orig_patent_app_number] => 09973815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973815
Transfer apparatus Oct 10, 2001 Issued
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