Search

Mary Ann Calabrese

Examiner (ID: 18530, Phone: (571)272-8704 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2931, 2913
Total Applications
4141
Issued Applications
3855
Pending Applications
21
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1570159 [patent_doc_number] => 06498052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Circuit, method of adhering an integrated circuit device to a substrate, and method of forming a circuit' [patent_app_type] => B2 [patent_app_number] => 09/974001 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3741 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498052.pdf [firstpage_image] =>[orig_patent_app_number] => 09974001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974001
Circuit, method of adhering an integrated circuit device to a substrate, and method of forming a circuit Oct 8, 2001 Issued
Array ( [id] => 5921980 [patent_doc_number] => 20020115238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'STITCHED PLANE STRUCTURE FOR PACKAGE POWER DELIVERY AND DUAL REFERENCED STRIPLINE I/O PERFORMANCE' [patent_app_type] => new [patent_app_number] => 09/972532 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2814 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20020115238.pdf [firstpage_image] =>[orig_patent_app_number] => 09972532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972532
Stitched plane structure for package power delivery and dual referenced stripline I/O performance Oct 4, 2001 Issued
Array ( [id] => 7450104 [patent_doc_number] => 20040067612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Miniaturised ldd-type mos transistors' [patent_app_type] => new [patent_app_number] => 10/257209 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2639 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067612.pdf [firstpage_image] =>[orig_patent_app_number] => 10257209 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/257209
LDD-type miniaturized MOS transistors Oct 4, 2001 Issued
Array ( [id] => 6032967 [patent_doc_number] => 20020019075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'METHODS OF FORMING A CIRCUIT AND METHODS OF PREPARING AN INTEGRATED CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/971819 [patent_app_country] => US [patent_app_date] => 2001-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3728 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019075.pdf [firstpage_image] =>[orig_patent_app_number] => 09971819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971819
Methods of forming a circuit and methods of preparing an integrated circuit Oct 2, 2001 Issued
Array ( [id] => 6781122 [patent_doc_number] => 20030062569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'SELF-ALIGNED DUAL-OXIDE UMOSFET DEVICE AND A METHOD OF FABRICATING SAME' [patent_app_type] => new [patent_app_number] => 09/968142 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062569.pdf [firstpage_image] =>[orig_patent_app_number] => 09968142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/968142
Self-aligned dual-oxide umosfet device and a method of fabricating same Sep 30, 2001 Issued
Array ( [id] => 1588812 [patent_doc_number] => 06482703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method for fabricating an electrostatic discharge device in a dual gate oxide process' [patent_app_type] => B1 [patent_app_number] => 09/965322 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2057 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482703.pdf [firstpage_image] =>[orig_patent_app_number] => 09965322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965322
Method for fabricating an electrostatic discharge device in a dual gate oxide process Sep 27, 2001 Issued
Array ( [id] => 1205645 [patent_doc_number] => 06716734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Low temperature sidewall oxidation of W/WN/poly-gatestack' [patent_app_type] => B2 [patent_app_number] => 09/965092 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1672 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716734.pdf [firstpage_image] =>[orig_patent_app_number] => 09965092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965092
Low temperature sidewall oxidation of W/WN/poly-gatestack Sep 27, 2001 Issued
Array ( [id] => 1324153 [patent_doc_number] => 06606135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Optical lens system, image display apparatus, micro-lens array, liquid crystal display device, and liquid crystal display apparatus of projection-type' [patent_app_type] => B2 [patent_app_number] => 09/964520 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 12387 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606135.pdf [firstpage_image] =>[orig_patent_app_number] => 09964520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964520
Optical lens system, image display apparatus, micro-lens array, liquid crystal display device, and liquid crystal display apparatus of projection-type Sep 27, 2001 Issued
Array ( [id] => 1277884 [patent_doc_number] => 06645840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Multi-layered polysilicon process' [patent_app_type] => B2 [patent_app_number] => 09/967061 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1741 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645840.pdf [firstpage_image] =>[orig_patent_app_number] => 09967061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967061
Multi-layered polysilicon process Sep 27, 2001 Issued
Array ( [id] => 1285346 [patent_doc_number] => 06638860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method and apparatus for processing substrates and method for manufacturing a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/963382 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7465 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638860.pdf [firstpage_image] =>[orig_patent_app_number] => 09963382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963382
Method and apparatus for processing substrates and method for manufacturing a semiconductor device Sep 26, 2001 Issued
Array ( [id] => 6209359 [patent_doc_number] => 20020072211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method of manufacturing semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/962112 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4232 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072211.pdf [firstpage_image] =>[orig_patent_app_number] => 09962112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962112
Method of manufacturing semiconductor devices Sep 25, 2001 Issued
Array ( [id] => 1358924 [patent_doc_number] => 06573169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Highly conductive composite polysilicon gate for CMOS integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/964172 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3834 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573169.pdf [firstpage_image] =>[orig_patent_app_number] => 09964172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964172
Highly conductive composite polysilicon gate for CMOS integrated circuits Sep 25, 2001 Issued
Array ( [id] => 5874012 [patent_doc_number] => 20020048855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/961361 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8645 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048855.pdf [firstpage_image] =>[orig_patent_app_number] => 09961361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961361
Semiconductor device and method of manufacturing the same Sep 24, 2001 Issued
Array ( [id] => 1214275 [patent_doc_number] => 06710424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'RF chipset architecture' [patent_app_type] => B2 [patent_app_number] => 09/962717 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4242 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/710/06710424.pdf [firstpage_image] =>[orig_patent_app_number] => 09962717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962717
RF chipset architecture Sep 20, 2001 Issued
Array ( [id] => 6405959 [patent_doc_number] => 20020037631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Method for manufacturing semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/961222 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3390 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037631.pdf [firstpage_image] =>[orig_patent_app_number] => 09961222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961222
Method for manufacturing semiconductor devices Sep 20, 2001 Abandoned
Array ( [id] => 6123428 [patent_doc_number] => 20020074612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Fabrication of field-effect transistor for alleviating short-channel effects and/or reducing junction capacitance' [patent_app_type] => new [patent_app_number] => 09/947012 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 48517 [patent_no_of_claims] => 94 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074612.pdf [firstpage_image] =>[orig_patent_app_number] => 09947012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947012
Fabrication of field-effect transistor for alleviating short-channel effects Sep 3, 2001 Issued
Array ( [id] => 1507339 [patent_doc_number] => 06440804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Static random access memory manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/945052 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440804.pdf [firstpage_image] =>[orig_patent_app_number] => 09945052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945052
Static random access memory manufacturing method Aug 30, 2001 Issued
Array ( [id] => 6750540 [patent_doc_number] => 20030045060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Crystalline or amorphous medium-k gate oxides, Y2O3 and Gd2O3' [patent_app_type] => new [patent_app_number] => 09/944981 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5121 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045060.pdf [firstpage_image] =>[orig_patent_app_number] => 09944981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944981
Gate oxides, and methods of forming Aug 29, 2001 Issued
Array ( [id] => 6690892 [patent_doc_number] => 20030038324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'NMOSFET with negative voltage capability formed in P-type substrate and method of making the \nsame' [patent_app_type] => new [patent_app_number] => 09/939552 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038324.pdf [firstpage_image] =>[orig_patent_app_number] => 09939552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939552
NMOSFET with negative voltage capability formed in P-type substrate and method of making the same Aug 26, 2001 Issued
Array ( [id] => 7400903 [patent_doc_number] => 20040023519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Single molecule array on silicon substrate for quantum computer' [patent_app_type] => new [patent_app_number] => 10/362821 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6696 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023519.pdf [firstpage_image] =>[orig_patent_app_number] => 10362821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362821
Single molecule array on silicon substrate for quantum computer Aug 23, 2001 Issued
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