Mary Ann Calabrese

Array ( [id] => 6410754 [patent_doc_number] => 20100140808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Power Distribution In A Vertically Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/703365 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140808.pdf [firstpage_image] =>[orig_patent_app_number] => 12703365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8214016 [patent_doc_number] => 08193040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Manufacturing of a device including a semiconductor chip' [patent_app_type] => utility [patent_app_number] => 12/701779 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 36 [patent_no_of_words] => 7810 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193040.pdf [firstpage_image] =>[orig_patent_app_number] => 12701779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8214135 [patent_doc_number] => 08193098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/700957 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193098.pdf [firstpage_image] =>[orig_patent_app_number] => 12700957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111710 [patent_doc_number] => 20110189827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHOD OF FABRICATING EFUSE STRUCTURE, RESISTOR STURCTURE AND TRANSISTOR STURCTURE' [patent_app_type] => utility [patent_app_number] => 12/700707 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20110189827.pdf [firstpage_image] =>[orig_patent_app_number] => 12700707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6119723 [patent_doc_number] => 20110076828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/700088 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20110076828.pdf [firstpage_image] =>[orig_patent_app_number] => 12700088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7729407 [patent_doc_number] => 08101482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method of fabricating semiconductor device having transistor' [patent_app_type] => utility [patent_app_number] => 12/656544 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4471 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/101/08101482.pdf [firstpage_image] =>[orig_patent_app_number] => 12656544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7540237 [patent_doc_number] => 08058080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Method of manufacturing a magnetic random access memory, method of manufacturing an embedded memory, and template' [patent_app_type] => utility [patent_app_number] => 12/699721 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 42 [patent_no_of_words] => 6564 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/058/08058080.pdf [firstpage_image] =>[orig_patent_app_number] => 12699721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6494016 [patent_doc_number] => 20100200869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'METHOD OF MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/698306 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 12785 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200869.pdf [firstpage_image] =>[orig_patent_app_number] => 12698306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6202467 [patent_doc_number] => 20110065253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'MANUFACTURING METHOD FOR DOUBLE-SIDE CAPACITOR OF STACK DRAM' [patent_app_type] => utility [patent_app_number] => 12/698322 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20110065253.pdf [firstpage_image] =>[orig_patent_app_number] => 12698322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111639 [patent_doc_number] => 20110189802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHOD FOR ENHANCING LIGHT EXTRACTION EFFICIENCY OF LIGHT EMITTING DIODES' [patent_app_type] => utility [patent_app_number] => 12/697414 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 3727 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20110189802.pdf [firstpage_image] =>[orig_patent_app_number] => 12697414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7535185 [patent_doc_number] => 08048810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Method for metal gate N/P patterning' [patent_app_type] => utility [patent_app_number] => 12/696252 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/048/08048810.pdf [firstpage_image] =>[orig_patent_app_number] => 12696252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6311290 [patent_doc_number] => 20100193914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Semiconductor device, method of manufacturing the same, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 12/657799 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5872 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20100193914.pdf [firstpage_image] =>[orig_patent_app_number] => 12657799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6500938 [patent_doc_number] => 20100210057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Method for Manufacturing Thin Film Transistor and Method for Manufacturing Display Device' [patent_app_type] => utility [patent_app_number] => 12/695802 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 23503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20100210057.pdf [firstpage_image] =>[orig_patent_app_number] => 12695802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6501040 [patent_doc_number] => 20100210070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR HAVING AN OXIDE SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 12/695361 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11415 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20100210070.pdf [firstpage_image] =>[orig_patent_app_number] => 12695361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6230441 [patent_doc_number] => 20100184245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'METHOD FOR MANUFACTURING A BOLOMETRIC DETECTOR' [patent_app_type] => utility [patent_app_number] => 12/686103 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5642 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20100184245.pdf [firstpage_image] =>[orig_patent_app_number] => 12686103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7490514 [patent_doc_number] => 08030196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Transistor formation using capping layer' [patent_app_type] => utility [patent_app_number] => 12/685933 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 55 [patent_no_of_words] => 9457 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030196.pdf [firstpage_image] =>[orig_patent_app_number] => 12685933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6240293 [patent_doc_number] => 20100133661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS' [patent_app_type] => utility [patent_app_number] => 12/648864 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7225 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133661.pdf [firstpage_image] =>[orig_patent_app_number] => 12648864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4510291 [patent_doc_number] => RE042332 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Integrated circuit package, ball-grid array integrated circuit package' [patent_app_type] => reissue [patent_app_number] => 12/629951 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3385 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042332.pdf [firstpage_image] =>[orig_patent_app_number] => 12629951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4532773 [patent_doc_number] => RE042457 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Methods of packaging an integrated circuit and methods of forming an integrated circuit package' [patent_app_type] => reissue [patent_app_number] => 12/629769 [patent_app_country] => US [patent_app_date] => 2009-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3320 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042457.pdf [firstpage_image] =>[orig_patent_app_number] => 12629769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4513985 [patent_doc_number] => 07910414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Method of fabricating array substrate' [patent_app_type] => utility [patent_app_number] => 12/591501 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5460 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/910/07910414.pdf [firstpage_image] =>[orig_patent_app_number] => 12591501 [rel_patent_id] =>[rel_patent_doc_number] =>)