Mary Ann Calabrese

Array ( [id] => 6838873 [patent_doc_number] => 20030036213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Optical switch with multiplexed data and control signals separated by group velocity dispersion' [patent_app_type] => new [patent_app_number] => 09/930308 [patent_app_country] => US [patent_app_date] => 2001-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19438 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20030036213.pdf [firstpage_image] =>[orig_patent_app_number] => 09930308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6063122 [patent_doc_number] => 20020031649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Quantum dot of single electron memory device and method for fabricationg thereof' [patent_app_type] => new [patent_app_number] => 09/929511 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4124 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031649.pdf [firstpage_image] =>[orig_patent_app_number] => 09929511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1248188 [patent_doc_number] => 06673667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials' [patent_app_type] => B2 [patent_app_number] => 09/929021 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 47 [patent_no_of_words] => 12912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673667.pdf [firstpage_image] =>[orig_patent_app_number] => 09929021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1184775 [patent_doc_number] => 06738117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Liquid crystal display device' [patent_app_type] => B2 [patent_app_number] => 09/929067 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5107 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738117.pdf [firstpage_image] =>[orig_patent_app_number] => 09929067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1346185 [patent_doc_number] => 06583015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Gate technology for strained surface channel and strained buried channel MOSFET devices' [patent_app_type] => B2 [patent_app_number] => 09/923207 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4255 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583015.pdf [firstpage_image] =>[orig_patent_app_number] => 09923207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466903 [patent_doc_number] => 06458621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Batch fabricated molecular electronic devices with cost-effective lithographic electrodes' [patent_app_type] => B1 [patent_app_number] => 09/920994 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 6738 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458621.pdf [firstpage_image] =>[orig_patent_app_number] => 09920994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6861280 [patent_doc_number] => 20030092288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Method and apparatus for removing unwanted substance from semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/258792 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6470 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20030092288.pdf [firstpage_image] =>[orig_patent_app_number] => 10258792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1256026 [patent_doc_number] => 06667196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method' [patent_app_type] => B2 [patent_app_number] => 09/911507 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 48 [patent_no_of_words] => 15279 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667196.pdf [firstpage_image] =>[orig_patent_app_number] => 09911507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6745283 [patent_doc_number] => 20030022466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Structure and method for fabricating semiconductor structure and linearized monolithic power amplifier utilizing the formation of a compliant substrate for materials used to form the same' [patent_app_type] => new [patent_app_number] => 09/911446 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 21372 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022466.pdf [firstpage_image] =>[orig_patent_app_number] => 09911446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6772364 [patent_doc_number] => 20030015702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same' [patent_app_type] => new [patent_app_number] => 09/908707 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8434 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015702.pdf [firstpage_image] =>[orig_patent_app_number] => 09908707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1574711 [patent_doc_number] => 06468877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner' [patent_app_type] => B1 [patent_app_number] => 09/907651 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468877.pdf [firstpage_image] =>[orig_patent_app_number] => 09907651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6774384 [patent_doc_number] => 20030017722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Structure and method for fabricating an integrated phased array circuit' [patent_app_type] => new [patent_app_number] => 09/905933 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19966 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20030017722.pdf [firstpage_image] =>[orig_patent_app_number] => 09905933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6735588 [patent_doc_number] => 20030013223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant III-V arsenide nitride substrate used to form the same' [patent_app_type] => new [patent_app_number] => 09/904892 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9441 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20030013223.pdf [firstpage_image] =>[orig_patent_app_number] => 09904892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6735583 [patent_doc_number] => 20030013218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Structure and method for fabricating semiconductor structures and devices for detecting chemical reactant' [patent_app_type] => new [patent_app_number] => 09/900883 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17955 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20030013218.pdf [firstpage_image] =>[orig_patent_app_number] => 09900883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1532601 [patent_doc_number] => 06410426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Damascene cap layer process for integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/901392 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1964 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410426.pdf [firstpage_image] =>[orig_patent_app_number] => 09901392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507416 [patent_doc_number] => 06440832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Hybrid MOS and schottky gate technology' [patent_app_type] => B1 [patent_app_number] => 09/900311 [patent_app_country] => US [patent_app_date] => 2001-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440832.pdf [firstpage_image] =>[orig_patent_app_number] => 09900311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6651511 [patent_doc_number] => 20030008527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate and laser radiation for materials used to form the same' [patent_app_type] => new [patent_app_number] => 09/897128 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10664 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008527.pdf [firstpage_image] =>[orig_patent_app_number] => 09897128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466946 [patent_doc_number] => 06458643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method of fabricating a MOS device with an ultra-shallow junction' [patent_app_type] => B1 [patent_app_number] => 09/681984 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2335 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458643.pdf [firstpage_image] =>[orig_patent_app_number] => 09681984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602561 [patent_doc_number] => 06432740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Fabrication of molecular electronic circuit by imprinting' [patent_app_type] => B1 [patent_app_number] => 09/895601 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3165 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432740.pdf [firstpage_image] =>[orig_patent_app_number] => 09895601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1399248 [patent_doc_number] => 06537901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method of manufacturing a transistor in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/887511 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5075 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537901.pdf [firstpage_image] =>[orig_patent_app_number] => 09887511 [rel_patent_id] =>[rel_patent_doc_number] =>)