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Maryam Nmn Emadi

Examiner (ID: 10057)

Most Active Art Unit
2478
Art Unit(s)
2478
Total Applications
28
Issued Applications
2
Pending Applications
26
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2553816 [patent_doc_number] => 04803180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-07 [patent_title] => 'Method for manufacturing pressure contact semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/056990 [patent_app_country] => US [patent_app_date] => 1987-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1513 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/803/04803180.pdf [firstpage_image] =>[orig_patent_app_number] => 056990 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/056990
Method for manufacturing pressure contact semiconductor devices Jun 2, 1987 Issued
Array ( [id] => 2503455 [patent_doc_number] => 04798794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-17 [patent_title] => 'Method for manufacturing dynamic memory cell' [patent_app_type] => 1 [patent_app_number] => 7/056726 [patent_app_country] => US [patent_app_date] => 1987-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5118 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/798/04798794.pdf [firstpage_image] =>[orig_patent_app_number] => 056726 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/056726
Method for manufacturing dynamic memory cell Jun 1, 1987 Issued
Array ( [id] => 2451105 [patent_doc_number] => 04760032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-07-26 [patent_title] => 'Screening of gate oxides on semiconductors' [patent_app_type] => 1 [patent_app_number] => 7/055335 [patent_app_country] => US [patent_app_date] => 1987-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2452 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/760/04760032.pdf [firstpage_image] =>[orig_patent_app_number] => 055335 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/055335
Screening of gate oxides on semiconductors May 28, 1987 Issued
Array ( [id] => 2479312 [patent_doc_number] => 04820402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Hydrocracking process with improved distillate selectivity with high silica large pore zeolites' [patent_app_type] => 1 [patent_app_number] => 7/056341 [patent_app_country] => US [patent_app_date] => 1987-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 7402 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/820/04820402.pdf [firstpage_image] =>[orig_patent_app_number] => 056341 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/056341
Hydrocracking process with improved distillate selectivity with high silica large pore zeolites May 26, 1987 Issued
Array ( [id] => 2484283 [patent_doc_number] => 04820657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Method for altering characteristics of junction semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/053475 [patent_app_country] => US [patent_app_date] => 1987-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5089 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/820/04820657.pdf [firstpage_image] =>[orig_patent_app_number] => 053475 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/053475
Method for altering characteristics of junction semiconductor devices May 25, 1987 Issued
07/053474 METHOD FOR ALTERING CHARACTERISTICS OF ACTIVE SEMICONDUCTOR DEVICES May 25, 1987 Abandoned
Array ( [id] => 2387640 [patent_doc_number] => 04772565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-20 [patent_title] => 'Method of manufacturing solid-state image sensor' [patent_app_type] => 1 [patent_app_number] => 7/051590 [patent_app_country] => US [patent_app_date] => 1987-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2856 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/772/04772565.pdf [firstpage_image] =>[orig_patent_app_number] => 051590 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/051590
Method of manufacturing solid-state image sensor May 19, 1987 Issued
Array ( [id] => 2491071 [patent_doc_number] => 04843022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-27 [patent_title] => 'Method of making fibrous silicon semiconductor by plasma CVD' [patent_app_type] => 1 [patent_app_number] => 7/051170 [patent_app_country] => US [patent_app_date] => 1987-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 9102 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/843/04843022.pdf [firstpage_image] =>[orig_patent_app_number] => 051170 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/051170
Method of making fibrous silicon semiconductor by plasma CVD May 17, 1987 Issued
Array ( [id] => 2395503 [patent_doc_number] => 04741077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-03 [patent_title] => 'End terminations for capacitors' [patent_app_type] => 1 [patent_app_number] => 7/050883 [patent_app_country] => US [patent_app_date] => 1987-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4949 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/741/04741077.pdf [firstpage_image] =>[orig_patent_app_number] => 050883 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050883
End terminations for capacitors May 14, 1987 Issued
Array ( [id] => 2490350 [patent_doc_number] => 04829019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-09 [patent_title] => 'Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment' [patent_app_type] => 1 [patent_app_number] => 7/048719 [patent_app_country] => US [patent_app_date] => 1987-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2118 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/829/04829019.pdf [firstpage_image] =>[orig_patent_app_number] => 048719 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/048719
Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment May 11, 1987 Issued
Array ( [id] => 2384164 [patent_doc_number] => 04775640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-04 [patent_title] => 'Electronic device test method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/044626 [patent_app_country] => US [patent_app_date] => 1987-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2987 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/775/04775640.pdf [firstpage_image] =>[orig_patent_app_number] => 044626 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/044626
Electronic device test method and apparatus Apr 30, 1987 Issued
Array ( [id] => 2546401 [patent_doc_number] => 04810667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-07 [patent_title] => 'Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer' [patent_app_type] => 1 [patent_app_number] => 7/043510 [patent_app_country] => US [patent_app_date] => 1987-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1949 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/810/04810667.pdf [firstpage_image] =>[orig_patent_app_number] => 043510 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/043510
Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer Apr 27, 1987 Issued
Array ( [id] => 2456755 [patent_doc_number] => 04784969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-15 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/043444 [patent_app_country] => US [patent_app_date] => 1987-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/784/04784969.pdf [firstpage_image] =>[orig_patent_app_number] => 043444 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/043444
Method of manufacturing a semiconductor memory device Apr 27, 1987 Issued
Array ( [id] => 2425683 [patent_doc_number] => 04750256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-14 [patent_title] => 'Method of assembly of an O.sub.2 sensor' [patent_app_type] => 1 [patent_app_number] => 7/037368 [patent_app_country] => US [patent_app_date] => 1987-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4567 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 511 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/750/04750256.pdf [firstpage_image] =>[orig_patent_app_number] => 037368 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/037368
Method of assembly of an O.sub.2 sensor Apr 12, 1987 Issued
07/036405 VERTICAL DRAM CELL AND METHOD Apr 8, 1987 Abandoned
Array ( [id] => 2526196 [patent_doc_number] => 04797375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-10 [patent_title] => 'Fabrication of metal interconnect for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/036185 [patent_app_country] => US [patent_app_date] => 1987-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1368 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/797/04797375.pdf [firstpage_image] =>[orig_patent_app_number] => 036185 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/036185
Fabrication of metal interconnect for semiconductor device Apr 8, 1987 Issued
Array ( [id] => 2445865 [patent_doc_number] => 04791072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-13 [patent_title] => 'Method for making a complementary device containing MODFET' [patent_app_type] => 1 [patent_app_number] => 7/036162 [patent_app_country] => US [patent_app_date] => 1987-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2385 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/791/04791072.pdf [firstpage_image] =>[orig_patent_app_number] => 036162 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/036162
Method for making a complementary device containing MODFET Apr 6, 1987 Issued
Array ( [id] => 2388442 [patent_doc_number] => 04764477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-16 [patent_title] => 'CMOS process flow with small gate geometry LDO N-channel transistors' [patent_app_type] => 1 [patent_app_number] => 7/034197 [patent_app_country] => US [patent_app_date] => 1987-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2873 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/764/04764477.pdf [firstpage_image] =>[orig_patent_app_number] => 034197 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/034197
CMOS process flow with small gate geometry LDO N-channel transistors Apr 5, 1987 Issued
Array ( [id] => 2384624 [patent_doc_number] => 04729971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-03-08 [patent_title] => 'Semiconductor wafer dicing techniques' [patent_app_type] => 1 [patent_app_number] => 7/033132 [patent_app_country] => US [patent_app_date] => 1987-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2364 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/729/04729971.pdf [firstpage_image] =>[orig_patent_app_number] => 033132 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/033132
Semiconductor wafer dicing techniques Mar 30, 1987 Issued
Array ( [id] => 2450460 [patent_doc_number] => 04732868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-03-22 [patent_title] => 'Method of manufacture of a uniphase CCD' [patent_app_type] => 1 [patent_app_number] => 7/031974 [patent_app_country] => US [patent_app_date] => 1987-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2619 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/732/04732868.pdf [firstpage_image] =>[orig_patent_app_number] => 031974 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/031974
Method of manufacture of a uniphase CCD Mar 29, 1987 Issued
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