Maryam Nmn Emadi
Examiner (ID: 10057)
Most Active Art Unit | 2478 |
Art Unit(s) | 2478 |
Total Applications | 28 |
Issued Applications | 2 |
Pending Applications | 26 |
Abandoned Applications | 0 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2626184
[patent_doc_number] => 04906585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches'
[patent_app_type] => 1
[patent_app_number] => 7/197663
[patent_app_country] => US
[patent_app_date] => 1988-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 2814
[patent_no_of_claims] => 9
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[patent_words_short_claim] => 218
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/906/04906585.pdf
[firstpage_image] =>[orig_patent_app_number] => 197663
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/197663 | Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches | May 19, 1988 | Issued |
Array
(
[id] => 2486749
[patent_doc_number] => 04846902
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-11
[patent_title] => 'Solid diffusion source of GD oxide/P205 compound and method of making silicon wafer'
[patent_app_type] => 1
[patent_app_number] => 7/195940
[patent_app_country] => US
[patent_app_date] => 1988-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
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[patent_no_of_words] => 1513
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[patent_words_short_claim] => 56
[patent_maintenance] => 1
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[pdf_file] => patents/04/846/04846902.pdf
[firstpage_image] =>[orig_patent_app_number] => 195940
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/195940 | Solid diffusion source of GD oxide/P205 compound and method of making silicon wafer | May 18, 1988 | Issued |
Array
(
[id] => 2626349
[patent_doc_number] => 04906594
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Surface smoothing method and method of forming SOI substrate using the surface smoothing method'
[patent_app_type] => 1
[patent_app_number] => 7/195124
[patent_app_country] => US
[patent_app_date] => 1988-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3463
[patent_no_of_claims] => 22
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[patent_words_short_claim] => 69
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/906/04906594.pdf
[firstpage_image] =>[orig_patent_app_number] => 195124
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/195124 | Surface smoothing method and method of forming SOI substrate using the surface smoothing method | May 15, 1988 | Issued |
Array
(
[id] => 2550990
[patent_doc_number] => 04814286
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-03-21
[patent_title] => 'EEPROM cell with integral select transistor'
[patent_app_type] => 1
[patent_app_number] => 7/192296
[patent_app_country] => US
[patent_app_date] => 1988-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3133
[patent_no_of_claims] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/814/04814286.pdf
[firstpage_image] =>[orig_patent_app_number] => 192296
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/192296 | EEPROM cell with integral select transistor | May 8, 1988 | Issued |
Array
(
[id] => 2465644
[patent_doc_number] => 04845055
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-04
[patent_title] => 'Rapid annealing under high pressure for use in fabrication of semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/194962
[patent_app_country] => US
[patent_app_date] => 1988-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2431
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/845/04845055.pdf
[firstpage_image] =>[orig_patent_app_number] => 194962
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/194962 | Rapid annealing under high pressure for use in fabrication of semiconductor device | May 6, 1988 | Issued |
Array
(
[id] => 2595468
[patent_doc_number] => 04911765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-27
[patent_title] => 'Method for fabricating a monolithic integration of a laser diode and a wide aperture photo diode'
[patent_app_type] => 1
[patent_app_number] => 7/189330
[patent_app_country] => US
[patent_app_date] => 1988-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 996
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/911/04911765.pdf
[firstpage_image] =>[orig_patent_app_number] => 189330
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/189330 | Method for fabricating a monolithic integration of a laser diode and a wide aperture photo diode | May 1, 1988 | Issued |
Array
(
[id] => 2492743
[patent_doc_number] => 04847214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-11
[patent_title] => 'Method for filling trenches from a seed layer'
[patent_app_type] => 1
[patent_app_number] => 7/182816
[patent_app_country] => US
[patent_app_date] => 1988-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3202
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/847/04847214.pdf
[firstpage_image] =>[orig_patent_app_number] => 182816
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/182816 | Method for filling trenches from a seed layer | Apr 17, 1988 | Issued |
07/183296 | SOI SEMICONDUCTOR DEVICES, INTEGRATED CIRCUITS AND METHODS OF FABRICATION | Apr 10, 1988 | Abandoned |
Array
(
[id] => 2557562
[patent_doc_number] => 04853340
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-01
[patent_title] => 'Semiconductor device isolated by a pair of field oxide regions'
[patent_app_type] => 1
[patent_app_number] => 7/176145
[patent_app_country] => US
[patent_app_date] => 1988-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3392
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
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[pdf_file] => patents/04/853/04853340.pdf
[firstpage_image] =>[orig_patent_app_number] => 176145
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/176145 | Semiconductor device isolated by a pair of field oxide regions | Mar 30, 1988 | Issued |
Array
(
[id] => 2607236
[patent_doc_number] => 04902635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-20
[patent_title] => 'Method for production of compound semicondutor devices'
[patent_app_type] => 1
[patent_app_number] => 7/175704
[patent_app_country] => US
[patent_app_date] => 1988-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1932
[patent_no_of_claims] => 15
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[pdf_file] => patents/04/902/04902635.pdf
[firstpage_image] =>[orig_patent_app_number] => 175704
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/175704 | Method for production of compound semicondutor devices | Mar 30, 1988 | Issued |
Array
(
[id] => 2552067
[patent_doc_number] => 04808544
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-28
[patent_title] => 'LDD structure containing conductive layer between gate oxide and sidewall spacer'
[patent_app_type] => 1
[patent_app_number] => 7/174494
[patent_app_country] => US
[patent_app_date] => 1988-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1403
[patent_no_of_claims] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/808/04808544.pdf
[firstpage_image] =>[orig_patent_app_number] => 174494
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/174494 | LDD structure containing conductive layer between gate oxide and sidewall spacer | Mar 27, 1988 | Issued |
Array
(
[id] => 2478084
[patent_doc_number] => 04876217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-24
[patent_title] => 'Method of forming semiconductor structure isolation regions'
[patent_app_type] => 1
[patent_app_number] => 7/173482
[patent_app_country] => US
[patent_app_date] => 1988-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 5187
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/876/04876217.pdf
[firstpage_image] =>[orig_patent_app_number] => 173482
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/173482 | Method of forming semiconductor structure isolation regions | Mar 23, 1988 | Issued |
Array
(
[id] => 2626170
[patent_doc_number] => 04966860
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-30
[patent_title] => 'Process for producing a SiC semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/172501
[patent_app_country] => US
[patent_app_date] => 1988-03-24
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/04/966/04966860.pdf
[firstpage_image] =>[orig_patent_app_number] => 172501
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/172501 | Process for producing a SiC semiconductor device | Mar 23, 1988 | Issued |
Array
(
[id] => 2486421
[patent_doc_number] => 04868136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-19
[patent_title] => 'Process of forming an isolation structure'
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[pdf_file] => patents/04/868/04868136.pdf
[firstpage_image] =>[orig_patent_app_number] => 178822
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/178822 | Process of forming an isolation structure | Mar 23, 1988 | Issued |
Array
(
[id] => 2634716
[patent_doc_number] => 04892835
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-09
[patent_title] => 'Method of manufacturing a field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/171990
[patent_app_country] => US
[patent_app_date] => 1988-03-23
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[pdf_file] => patents/04/892/04892835.pdf
[firstpage_image] =>[orig_patent_app_number] => 171990
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/171990 | Method of manufacturing a field effect transistor | Mar 22, 1988 | Issued |
Array
(
[id] => 2515726
[patent_doc_number] => 04863880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-05
[patent_title] => 'InSb device manufacturing by anodic oxidation'
[patent_app_type] => 1
[patent_app_number] => 7/171779
[patent_app_country] => US
[patent_app_date] => 1988-03-22
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[pdf_file] => patents/04/863/04863880.pdf
[firstpage_image] =>[orig_patent_app_number] => 171779
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/171779 | InSb device manufacturing by anodic oxidation | Mar 21, 1988 | Issued |
Array
(
[id] => 2511235
[patent_doc_number] => 04851363
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-25
[patent_title] => 'Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses'
[patent_app_type] => 1
[patent_app_number] => 7/171355
[patent_app_country] => US
[patent_app_date] => 1988-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/851/04851363.pdf
[firstpage_image] =>[orig_patent_app_number] => 171355
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/171355 | Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses | Mar 20, 1988 | Issued |
Array
(
[id] => 2482199
[patent_doc_number] => 04866002
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-12
[patent_title] => 'Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 7/171278
[patent_app_country] => US
[patent_app_date] => 1988-03-21
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/866/04866002.pdf
[firstpage_image] =>[orig_patent_app_number] => 171278
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/171278 | Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof | Mar 20, 1988 | Issued |
Array
(
[id] => 2666849
[patent_doc_number] => 04935378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-19
[patent_title] => 'Method for manufacturing a semiconductor device having more than two conductive layers'
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[pdf_file] => patents/04/935/04935378.pdf
[firstpage_image] =>[orig_patent_app_number] => 170253
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/170253 | Method for manufacturing a semiconductor device having more than two conductive layers | Mar 17, 1988 | Issued |
Array
(
[id] => 2557620
[patent_doc_number] => 04853343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-01
[patent_title] => 'Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill'
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[firstpage_image] =>[orig_patent_app_number] => 169748
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/169748 | Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill | Mar 17, 1988 | Issued |