Mathieu D Vargot
Examiner (ID: 8883, Phone: (571)272-1211 , Office: P/1742 )
Most Active Art Unit | 1732 |
Art Unit(s) | 1307, 1791, 1305, 1732, 1742, 2899 |
Total Applications | 3255 |
Issued Applications | 2227 |
Pending Applications | 219 |
Abandoned Applications | 809 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 653728
[patent_doc_number] => 07114114
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-09-26
[patent_title] => 'Dynamically reconfigurable precision signal delay test system for automatic test equipment'
[patent_app_type] => utility
[patent_app_number] => 10/917898
[patent_app_country] => US
[patent_app_date] => 2004-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 6465
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/114/07114114.pdf
[firstpage_image] =>[orig_patent_app_number] => 10917898
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/917898 | Dynamically reconfigurable precision signal delay test system for automatic test equipment | Aug 11, 2004 | Issued |
Array
(
[id] => 7000011
[patent_doc_number] => 20050138521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'FEC (Forward Error Correction) decoder with dynamic parameters'
[patent_app_type] => utility
[patent_app_number] => 10/916919
[patent_app_country] => US
[patent_app_date] => 2004-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 16140
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20050138521.pdf
[firstpage_image] =>[orig_patent_app_number] => 10916919
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/916919 | FEC (Forward Error Correction) decoder with dynamic parameters | Aug 11, 2004 | Issued |
Array
(
[id] => 5803646
[patent_doc_number] => 20060036931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'System and method for refreshing metric values'
[patent_app_type] => utility
[patent_app_number] => 10/915810
[patent_app_country] => US
[patent_app_date] => 2004-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5329
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20060036931.pdf
[firstpage_image] =>[orig_patent_app_number] => 10915810
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/915810 | System and method for refreshing metric values | Aug 10, 2004 | Issued |
Array
(
[id] => 6979711
[patent_doc_number] => 20050289429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Method and apparatus for decoding of turbo encoded data in a communication system'
[patent_app_type] => utility
[patent_app_number] => 10/915134
[patent_app_country] => US
[patent_app_date] => 2004-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5782
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20050289429.pdf
[firstpage_image] =>[orig_patent_app_number] => 10915134
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/915134 | Method and apparatus for decoding of turbo encoded data in a communication system | Aug 9, 2004 | Issued |
Array
(
[id] => 438527
[patent_doc_number] => 07263649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-28
[patent_title] => 'Converting circuit for preventing wrong error correction codes from occurring due to an error correction rule during data reading operation'
[patent_app_type] => utility
[patent_app_number] => 10/710860
[patent_app_country] => US
[patent_app_date] => 2004-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2024
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/263/07263649.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710860
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710860 | Converting circuit for preventing wrong error correction codes from occurring due to an error correction rule during data reading operation | Aug 8, 2004 | Issued |
Array
(
[id] => 431453
[patent_doc_number] => 07269759
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Data processing apparatus and method for handling corrupted data values'
[patent_app_type] => utility
[patent_app_number] => 10/912103
[patent_app_country] => US
[patent_app_date] => 2004-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 8380
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269759.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912103
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912103 | Data processing apparatus and method for handling corrupted data values | Aug 5, 2004 | Issued |
Array
(
[id] => 5882660
[patent_doc_number] => 20060031743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-09
[patent_title] => 'Method and apparatus for a modified parity check'
[patent_app_type] => utility
[patent_app_number] => 10/912483
[patent_app_country] => US
[patent_app_date] => 2004-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3319
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20060031743.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912483
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912483 | Method and apparatus for a modified parity check | Aug 4, 2004 | Issued |
Array
(
[id] => 430315
[patent_doc_number] => 07269187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Packet detection system and method'
[patent_app_type] => utility
[patent_app_number] => 10/911854
[patent_app_country] => US
[patent_app_date] => 2004-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4046
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269187.pdf
[firstpage_image] =>[orig_patent_app_number] => 10911854
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911854 | Packet detection system and method | Aug 4, 2004 | Issued |
Array
(
[id] => 7000020
[patent_doc_number] => 20050138530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Data compression with incremental redundancy'
[patent_app_type] => utility
[patent_app_number] => 10/911297
[patent_app_country] => US
[patent_app_date] => 2004-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6065
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20050138530.pdf
[firstpage_image] =>[orig_patent_app_number] => 10911297
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911297 | Data compression with incremental redundancy | Aug 3, 2004 | Issued |
Array
(
[id] => 458651
[patent_doc_number] => 07245244
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-07-17
[patent_title] => 'Correction methods and structures for analog-to-digital converter transfer functions'
[patent_app_type] => utility
[patent_app_number] => 10/911314
[patent_app_country] => US
[patent_app_date] => 2004-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2778
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/245/07245244.pdf
[firstpage_image] =>[orig_patent_app_number] => 10911314
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911314 | Correction methods and structures for analog-to-digital converter transfer functions | Aug 2, 2004 | Issued |
Array
(
[id] => 462462
[patent_doc_number] => 07242325
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-10
[patent_title] => 'Error correction compensating ones or zeros string suppression'
[patent_app_type] => utility
[patent_app_number] => 10/910433
[patent_app_country] => US
[patent_app_date] => 2004-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4380
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/242/07242325.pdf
[firstpage_image] =>[orig_patent_app_number] => 10910433
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/910433 | Error correction compensating ones or zeros string suppression | Aug 1, 2004 | Issued |
Array
(
[id] => 5770883
[patent_doc_number] => 20060020873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Error correction code generation method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/896217
[patent_app_country] => US
[patent_app_date] => 2004-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4736
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0020/20060020873.pdf
[firstpage_image] =>[orig_patent_app_number] => 10896217
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/896217 | Error correction code generation method and apparatus | Jul 20, 2004 | Issued |
Array
(
[id] => 400694
[patent_doc_number] => 07296208
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Method and system for generating parallel decodable low density parity check (LDPC) codes'
[patent_app_type] => utility
[patent_app_number] => 10/882705
[patent_app_country] => US
[patent_app_date] => 2004-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7769
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/296/07296208.pdf
[firstpage_image] =>[orig_patent_app_number] => 10882705
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/882705 | Method and system for generating parallel decodable low density parity check (LDPC) codes | Jun 30, 2004 | Issued |
Array
(
[id] => 6979725
[patent_doc_number] => 20050289443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Method and apparatus for additive trellis encoding'
[patent_app_type] => utility
[patent_app_number] => 10/879395
[patent_app_country] => US
[patent_app_date] => 2004-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 8134
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20050289443.pdf
[firstpage_image] =>[orig_patent_app_number] => 10879395
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879395 | Method and apparatus for additive trellis encoding | Jun 28, 2004 | Issued |
Array
(
[id] => 431504
[patent_doc_number] => 07269781
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Discrete universal denoising with reliability information'
[patent_app_type] => utility
[patent_app_number] => 10/876958
[patent_app_country] => US
[patent_app_date] => 2004-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 11392
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269781.pdf
[firstpage_image] =>[orig_patent_app_number] => 10876958
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/876958 | Discrete universal denoising with reliability information | Jun 24, 2004 | Issued |
Array
(
[id] => 7262596
[patent_doc_number] => 20040261006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Rate dematching processor'
[patent_app_type] => new
[patent_app_number] => 10/869079
[patent_app_country] => US
[patent_app_date] => 2004-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9591
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20040261006.pdf
[firstpage_image] =>[orig_patent_app_number] => 10869079
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/869079 | Rate dematching processor | Jun 16, 2004 | Issued |
Array
(
[id] => 519190
[patent_doc_number] => 07203890
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-10
[patent_title] => 'Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits'
[patent_app_type] => utility
[patent_app_number] => 10/710066
[patent_app_country] => US
[patent_app_date] => 2004-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5790
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 522
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/203/07203890.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710066
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710066 | Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits | Jun 15, 2004 | Issued |
Array
(
[id] => 7266825
[patent_doc_number] => 20040243916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Method and apparatus for decoding multi-level trellis coded modulation'
[patent_app_type] => new
[patent_app_number] => 10/484183
[patent_app_country] => US
[patent_app_date] => 2004-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 5069
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0243/20040243916.pdf
[firstpage_image] =>[orig_patent_app_number] => 10484183
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/484183 | Method and apparatus for decoding multi-level trellis coded modulation | Jun 14, 2004 | Abandoned |
Array
(
[id] => 519034
[patent_doc_number] => 07203871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Arrangement in a network node for secure storage and retrieval of encoded data distributed among multiple network nodes'
[patent_app_type] => utility
[patent_app_number] => 10/859209
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5784
[patent_no_of_claims] => 72
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/203/07203871.pdf
[firstpage_image] =>[orig_patent_app_number] => 10859209
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859209 | Arrangement in a network node for secure storage and retrieval of encoded data distributed among multiple network nodes | Jun 2, 2004 | Issued |
Array
(
[id] => 922171
[patent_doc_number] => 07325165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-29
[patent_title] => 'Instruction sequence verification to protect secured data'
[patent_app_type] => utility
[patent_app_number] => 10/856882
[patent_app_country] => US
[patent_app_date] => 2004-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 25
[patent_no_of_words] => 8198
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/325/07325165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10856882
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/856882 | Instruction sequence verification to protect secured data | May 31, 2004 | Issued |