Search

Mathieu D Vargot

Examiner (ID: 8883, Phone: (571)272-1211 , Office: P/1742 )

Most Active Art Unit
1732
Art Unit(s)
1307, 1791, 1305, 1732, 1742, 2899
Total Applications
3255
Issued Applications
2227
Pending Applications
219
Abandoned Applications
809

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 782408 [patent_doc_number] => 06996766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Error detection/correction code which detects and corrects a first failing component and optionally a second failing component' [patent_app_type] => utility [patent_app_number] => 10/185959 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 19950 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996766.pdf [firstpage_image] =>[orig_patent_app_number] => 10185959 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185959
Error detection/correction code which detects and corrects a first failing component and optionally a second failing component Jun 27, 2002 Issued
Array ( [id] => 940545 [patent_doc_number] => 06973603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Method and apparatus for optimizing timing for a multi-drop bus' [patent_app_type] => utility [patent_app_number] => 10/187349 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1959 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973603.pdf [firstpage_image] =>[orig_patent_app_number] => 10187349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/187349
Method and apparatus for optimizing timing for a multi-drop bus Jun 27, 2002 Issued
Array ( [id] => 6659811 [patent_doc_number] => 20030079173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Trellis encoder with rate 1/4 and 1/2 for a backward compatible robust encoding ATSC DTV transmission system' [patent_app_type] => new [patent_app_number] => 10/183672 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20030079173.pdf [firstpage_image] =>[orig_patent_app_number] => 10183672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183672
Trellis encoder with rate 1/4 and 1/2 for a backward compatible robust encoding ATSC DTV transmission system Jun 26, 2002 Issued
Array ( [id] => 752811 [patent_doc_number] => 07028117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-11 [patent_title] => 'Structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter' [patent_app_type] => utility [patent_app_number] => 10/185875 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028117.pdf [firstpage_image] =>[orig_patent_app_number] => 10185875 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185875
Structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter Jun 26, 2002 Issued
Array ( [id] => 7260543 [patent_doc_number] => 20050076285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Error correction coding utilizing numerical base conversion for modulation coding' [patent_app_type] => utility [patent_app_number] => 10/184758 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9429 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20050076285.pdf [firstpage_image] =>[orig_patent_app_number] => 10184758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184758
Error correction coding utilizing numerical base conversion for modulation coding Jun 26, 2002 Issued
Array ( [id] => 684598 [patent_doc_number] => 07085864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter' [patent_app_type] => utility [patent_app_number] => 10/186102 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7302 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085864.pdf [firstpage_image] =>[orig_patent_app_number] => 10186102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186102
Method and structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter Jun 26, 2002 Issued
Array ( [id] => 1001860 [patent_doc_number] => 06912701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Method and apparatus for power supply noise modeling and test pattern development' [patent_app_type] => utility [patent_app_number] => 10/185866 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4036 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912701.pdf [firstpage_image] =>[orig_patent_app_number] => 10185866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185866
Method and apparatus for power supply noise modeling and test pattern development Jun 25, 2002 Issued
Array ( [id] => 7611288 [patent_doc_number] => 06904554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Logic built-in self test (BIST)' [patent_app_type] => utility [patent_app_number] => 10/180634 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7916 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904554.pdf [firstpage_image] =>[orig_patent_app_number] => 10180634 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180634
Logic built-in self test (BIST) Jun 25, 2002 Issued
Array ( [id] => 7446822 [patent_doc_number] => 20040003338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Powerline network flood control restriction' [patent_app_type] => new [patent_app_number] => 10/180171 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5517 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003338.pdf [firstpage_image] =>[orig_patent_app_number] => 10180171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180171
Powerline network flood control restriction Jun 25, 2002 Issued
Array ( [id] => 7446763 [patent_doc_number] => 20040003333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'System and method for transparent electronic data transfer using error correction to facilitate bandwidth-efficient data recovery' [patent_app_type] => new [patent_app_number] => 10/183581 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8206 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003333.pdf [firstpage_image] =>[orig_patent_app_number] => 10183581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183581
System and method for transparent electronic data transfer using error correction to facilitate bandwidth-efficient data recovery Jun 25, 2002 Issued
Array ( [id] => 765521 [patent_doc_number] => 07017092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'On-chip design for monitor' [patent_app_type] => utility [patent_app_number] => 10/178841 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3914 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017092.pdf [firstpage_image] =>[orig_patent_app_number] => 10178841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178841
On-chip design for monitor Jun 24, 2002 Issued
Array ( [id] => 953408 [patent_doc_number] => 06961882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Memory chip and apparatus for testing a memory chip' [patent_app_type] => utility [patent_app_number] => 10/179002 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2346 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961882.pdf [firstpage_image] =>[orig_patent_app_number] => 10179002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179002
Memory chip and apparatus for testing a memory chip Jun 24, 2002 Issued
Array ( [id] => 951721 [patent_doc_number] => 06960926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Method and apparatus for characterizing a circuit with multiple inputs' [patent_app_type] => utility [patent_app_number] => 10/178883 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4994 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960926.pdf [firstpage_image] =>[orig_patent_app_number] => 10178883 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178883
Method and apparatus for characterizing a circuit with multiple inputs Jun 23, 2002 Issued
Array ( [id] => 749584 [patent_doc_number] => 07032139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Bit error rate tester' [patent_app_type] => utility [patent_app_number] => 10/179760 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6483 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032139.pdf [firstpage_image] =>[orig_patent_app_number] => 10179760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179760
Bit error rate tester Jun 23, 2002 Issued
Array ( [id] => 731688 [patent_doc_number] => 07047460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method and apparatus for testing a storage interface' [patent_app_type] => utility [patent_app_number] => 10/179813 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047460.pdf [firstpage_image] =>[orig_patent_app_number] => 10179813 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179813
Method and apparatus for testing a storage interface Jun 23, 2002 Issued
Array ( [id] => 947752 [patent_doc_number] => 06966012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'Memory column redundancy circuitry and method for implementing the same' [patent_app_type] => utility [patent_app_number] => 10/179773 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7864 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/966/06966012.pdf [firstpage_image] =>[orig_patent_app_number] => 10179773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179773
Memory column redundancy circuitry and method for implementing the same Jun 23, 2002 Issued
Array ( [id] => 6336360 [patent_doc_number] => 20020199139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Test configuration for a parallel functional testing of semiconductor memory modules and test method' [patent_app_type] => new [patent_app_number] => 10/177887 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2284 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20020199139.pdf [firstpage_image] =>[orig_patent_app_number] => 10177887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177887
Test configuration for a parallel functional testing of semiconductor memory modules and test method Jun 19, 2002 Abandoned
Array ( [id] => 1210544 [patent_doc_number] => 06718504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method and apparatus for implementing a data processor adapted for turbo decoding' [patent_app_type] => B1 [patent_app_number] => 10/165146 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 13499 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718504.pdf [firstpage_image] =>[orig_patent_app_number] => 10165146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/165146
Method and apparatus for implementing a data processor adapted for turbo decoding Jun 4, 2002 Issued
Array ( [id] => 1087711 [patent_doc_number] => 06831901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'System and method for retransmission of data' [patent_app_type] => B2 [patent_app_number] => 10/161557 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8948 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831901.pdf [firstpage_image] =>[orig_patent_app_number] => 10161557 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161557
System and method for retransmission of data May 30, 2002 Issued
Array ( [id] => 6048365 [patent_doc_number] => 20020168945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Method for controlling data transmission in a radio communications system' [patent_app_type] => new [patent_app_number] => 10/142952 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6965 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20020168945.pdf [firstpage_image] =>[orig_patent_app_number] => 10142952 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/142952
Method for controlling data transmission in a radio communications system May 12, 2002 Issued
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