Search

Matthew C Graham

Examiner (ID: 12461, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3683, 3103, 3104, 2202, 3303, 3993
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1236243 [patent_doc_number] => 06694402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Access control for a memory having a limited erasure frequency' [patent_app_type] => B1 [patent_app_number] => 09/530704 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3314 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694402.pdf [firstpage_image] =>[orig_patent_app_number] => 09530704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/530704
Access control for a memory having a limited erasure frequency Jun 13, 2000 Issued
Array ( [id] => 1432377 [patent_doc_number] => 06505269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/571213 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505269.pdf [firstpage_image] =>[orig_patent_app_number] => 09571213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571213
Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system May 15, 2000 Issued
Array ( [id] => 1474908 [patent_doc_number] => 06408363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Speculative pre-flush of data in an out-of-order execution processor system' [patent_app_type] => B1 [patent_app_number] => 09/565013 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6641 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408363.pdf [firstpage_image] =>[orig_patent_app_number] => 09565013 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565013
Speculative pre-flush of data in an out-of-order execution processor system May 3, 2000 Issued
Array ( [id] => 1466260 [patent_doc_number] => 06393539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'System and method for reliably assigning and protecting data in a centralizes storage system' [patent_app_type] => B1 [patent_app_number] => 09/565020 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393539.pdf [firstpage_image] =>[orig_patent_app_number] => 09565020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565020
System and method for reliably assigning and protecting data in a centralizes storage system May 3, 2000 Issued
Array ( [id] => 999044 [patent_doc_number] => 06915395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Active address content addressable memory' [patent_app_type] => utility [patent_app_number] => 09/564202 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5466 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915395.pdf [firstpage_image] =>[orig_patent_app_number] => 09564202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564202
Active address content addressable memory May 2, 2000 Issued
Array ( [id] => 1347935 [patent_doc_number] => 06598135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'System and method for defining rewriteable data storage media as write once data storage media' [patent_app_type] => B1 [patent_app_number] => 09/564138 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4018 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598135.pdf [firstpage_image] =>[orig_patent_app_number] => 09564138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564138
System and method for defining rewriteable data storage media as write once data storage media May 2, 2000 Issued
Array ( [id] => 1210391 [patent_doc_number] => 06718452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Storage array supporting a plurality of instruction modes' [patent_app_type] => B1 [patent_app_number] => 09/563610 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4882 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718452.pdf [firstpage_image] =>[orig_patent_app_number] => 09563610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563610
Storage array supporting a plurality of instruction modes May 1, 2000 Issued
Array ( [id] => 1324060 [patent_doc_number] => 06611904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Memory access address comparison' [patent_app_type] => B1 [patent_app_number] => 09/563611 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4527 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611904.pdf [firstpage_image] =>[orig_patent_app_number] => 09563611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563611
Memory access address comparison May 1, 2000 Issued
Array ( [id] => 623247 [patent_doc_number] => 07143247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Method and apparatus for parallel execution pipeline data storage in a computer memory' [patent_app_type] => utility [patent_app_number] => 09/563315 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143247.pdf [firstpage_image] =>[orig_patent_app_number] => 09563315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563315
Method and apparatus for parallel execution pipeline data storage in a computer memory May 1, 2000 Issued
Array ( [id] => 1539161 [patent_doc_number] => 06412046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Verification of cache prefetch mechanism' [patent_app_type] => B1 [patent_app_number] => 09/562130 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4257 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412046.pdf [firstpage_image] =>[orig_patent_app_number] => 09562130 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562130
Verification of cache prefetch mechanism Apr 30, 2000 Issued
Array ( [id] => 1289067 [patent_doc_number] => 06647469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Using read current transactions for improved performance in directory-based coherent I/O systems' [patent_app_type] => B1 [patent_app_number] => 09/562191 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 13107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647469.pdf [firstpage_image] =>[orig_patent_app_number] => 09562191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562191
Using read current transactions for improved performance in directory-based coherent I/O systems Apr 30, 2000 Issued
Array ( [id] => 4424562 [patent_doc_number] => 06266752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache' [patent_app_type] => 1 [patent_app_number] => 9/550847 [patent_app_country] => US [patent_app_date] => 2000-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266752.pdf [firstpage_image] =>[orig_patent_app_number] => 550847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/550847
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache Apr 16, 2000 Issued
Array ( [id] => 1181006 [patent_doc_number] => 06754780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Providing data in response to a read command that maintains cache line alignment' [patent_app_type] => B1 [patent_app_number] => 09/542969 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6198 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754780.pdf [firstpage_image] =>[orig_patent_app_number] => 09542969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542969
Providing data in response to a read command that maintains cache line alignment Apr 3, 2000 Issued
Array ( [id] => 1337163 [patent_doc_number] => 06604179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Reading a FIFO in dual clock domains' [patent_app_type] => B2 [patent_app_number] => 09/532428 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5422 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604179.pdf [firstpage_image] =>[orig_patent_app_number] => 09532428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532428
Reading a FIFO in dual clock domains Mar 22, 2000 Issued
Array ( [id] => 563590 [patent_doc_number] => 07167964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-23 [patent_title] => 'Memory defragmentation in chipcards' [patent_app_type] => utility [patent_app_number] => 09/533731 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4211 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167964.pdf [firstpage_image] =>[orig_patent_app_number] => 09533731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533731
Memory defragmentation in chipcards Mar 22, 2000 Issued
Array ( [id] => 1508986 [patent_doc_number] => 06467016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Apparatus to record digital data on non-volatile memory card for recording in units of blocks of digital data and method thereof' [patent_app_type] => B1 [patent_app_number] => 09/532777 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 9406 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467016.pdf [firstpage_image] =>[orig_patent_app_number] => 09532777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532777
Apparatus to record digital data on non-volatile memory card for recording in units of blocks of digital data and method thereof Mar 21, 2000 Issued
Array ( [id] => 1297136 [patent_doc_number] => 06633962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method, system, program, and data structures for restricting host access to a storage space' [patent_app_type] => B1 [patent_app_number] => 09/531932 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7918 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633962.pdf [firstpage_image] =>[orig_patent_app_number] => 09531932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531932
Method, system, program, and data structures for restricting host access to a storage space Mar 20, 2000 Issued
Array ( [id] => 1501566 [patent_doc_number] => 06405293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Selectively accessible memory banks for operating in alternately reading or writing modes of operation' [patent_app_type] => B1 [patent_app_number] => 09/532372 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1023 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405293.pdf [firstpage_image] =>[orig_patent_app_number] => 09532372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532372
Selectively accessible memory banks for operating in alternately reading or writing modes of operation Mar 20, 2000 Issued
Array ( [id] => 1291818 [patent_doc_number] => 06643742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method and system for efficient cache memory updating with a least recently used (LRU) protocol' [patent_app_type] => B1 [patent_app_number] => 09/528748 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3969 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643742.pdf [firstpage_image] =>[orig_patent_app_number] => 09528748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528748
Method and system for efficient cache memory updating with a least recently used (LRU) protocol Mar 19, 2000 Issued
Array ( [id] => 4316389 [patent_doc_number] => 06199147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Distributed-memory multiprocessor computer system with directory-based cache coherency with ambiguous mappings of cached data to main-memory locations' [patent_app_type] => 1 [patent_app_number] => 9/528583 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7183 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199147.pdf [firstpage_image] =>[orig_patent_app_number] => 528583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528583
Distributed-memory multiprocessor computer system with directory-based cache coherency with ambiguous mappings of cached data to main-memory locations Mar 19, 2000 Issued
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