Search

Matthew C Graham

Examiner (ID: 12461, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3683, 3103, 3104, 2202, 3303, 3993
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1557496 [patent_doc_number] => 06401163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Apparatus and method for rewriting data from volatile memory to nonvolatile memory' [patent_app_type] => B1 [patent_app_number] => 09/321585 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2549 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401163.pdf [firstpage_image] =>[orig_patent_app_number] => 09321585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321585
Apparatus and method for rewriting data from volatile memory to nonvolatile memory May 27, 1999 Issued
Array ( [id] => 1438662 [patent_doc_number] => 06356976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'LSI system capable of reading and writing at high speed' [patent_app_type] => B1 [patent_app_number] => 09/286299 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9406 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356976.pdf [firstpage_image] =>[orig_patent_app_number] => 09286299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286299
LSI system capable of reading and writing at high speed Apr 5, 1999 Issued
Array ( [id] => 7608131 [patent_doc_number] => 07000069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Apparatus and method for providing very large virtual storage volumes using redundant arrays of disks' [patent_app_type] => utility [patent_app_number] => 09/286160 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000069.pdf [firstpage_image] =>[orig_patent_app_number] => 09286160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286160
Apparatus and method for providing very large virtual storage volumes using redundant arrays of disks Apr 4, 1999 Issued
Array ( [id] => 4416360 [patent_doc_number] => 06272053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Semiconductor device with common pin for address and data' [patent_app_type] => 1 [patent_app_number] => 9/283736 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2951 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272053.pdf [firstpage_image] =>[orig_patent_app_number] => 283736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283736
Semiconductor device with common pin for address and data Apr 1, 1999 Issued
Array ( [id] => 1533167 [patent_doc_number] => 06480946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Memory system for synchronized and high speed data transfer' [patent_app_type] => B1 [patent_app_number] => 09/283758 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 63 [patent_no_of_words] => 30861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480946.pdf [firstpage_image] =>[orig_patent_app_number] => 09283758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283758
Memory system for synchronized and high speed data transfer Apr 1, 1999 Issued
Array ( [id] => 4298466 [patent_doc_number] => 06282606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods' [patent_app_type] => 1 [patent_app_number] => 9/285869 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3191 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282606.pdf [firstpage_image] =>[orig_patent_app_number] => 285869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285869
Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods Apr 1, 1999 Issued
Array ( [id] => 1557566 [patent_doc_number] => 06401183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'System and method for operating system independent storage management' [patent_app_type] => B1 [patent_app_number] => 09/283418 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 7093 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401183.pdf [firstpage_image] =>[orig_patent_app_number] => 09283418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283418
System and method for operating system independent storage management Mar 31, 1999 Issued
Array ( [id] => 4399350 [patent_doc_number] => 06295591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of upgrading and/or servicing memory without interrupting the operation of the system' [patent_app_type] => 1 [patent_app_number] => 9/281084 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2405 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295591.pdf [firstpage_image] =>[orig_patent_app_number] => 281084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281084
Method of upgrading and/or servicing memory without interrupting the operation of the system Mar 29, 1999 Issued
Array ( [id] => 1584825 [patent_doc_number] => 06449699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-10 [patent_title] => 'Apparatus and method for partitioned memory protection in cache coherent symmetric multiprocessor systems' [patent_app_type] => B2 [patent_app_number] => 09/277934 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4506 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449699.pdf [firstpage_image] =>[orig_patent_app_number] => 09277934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277934
Apparatus and method for partitioned memory protection in cache coherent symmetric multiprocessor systems Mar 28, 1999 Issued
Array ( [id] => 4366318 [patent_doc_number] => 06286091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Microprocessor using TLB with tag indexes to access tag RAMs' [patent_app_type] => 1 [patent_app_number] => 9/280066 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3550 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286091.pdf [firstpage_image] =>[orig_patent_app_number] => 280066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280066
Microprocessor using TLB with tag indexes to access tag RAMs Mar 28, 1999 Issued
Array ( [id] => 4374102 [patent_doc_number] => 06292876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for providing access protection for SCSI storage devices' [patent_app_type] => 1 [patent_app_number] => 9/249494 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2761 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292876.pdf [firstpage_image] =>[orig_patent_app_number] => 249494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249494
Method for providing access protection for SCSI storage devices Feb 11, 1999 Issued
Array ( [id] => 4333144 [patent_doc_number] => 06332175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Low power system and method for playing compressed audio data' [patent_app_type] => 1 [patent_app_number] => 9/249183 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4872 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332175.pdf [firstpage_image] =>[orig_patent_app_number] => 249183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249183
Low power system and method for playing compressed audio data Feb 11, 1999 Issued
Array ( [id] => 1438672 [patent_doc_number] => 06356981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method and apparatus for preserving data coherency in a double data rate SRAM' [patent_app_type] => B1 [patent_app_number] => 09/250772 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3420 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356981.pdf [firstpage_image] =>[orig_patent_app_number] => 09250772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250772
Method and apparatus for preserving data coherency in a double data rate SRAM Feb 11, 1999 Issued
Array ( [id] => 1573788 [patent_doc_number] => 06499095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Machine-independent memory management system within a run-time environment' [patent_app_type] => B1 [patent_app_number] => 09/248291 [patent_app_country] => US [patent_app_date] => 1999-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 10220 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499095.pdf [firstpage_image] =>[orig_patent_app_number] => 09248291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/248291
Machine-independent memory management system within a run-time environment Feb 10, 1999 Issued
Array ( [id] => 6561241 [patent_doc_number] => 20020138704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'METHOD AND APPARATUS FAULT TOLERANT SHARED MEMORY' [patent_app_type] => new [patent_app_number] => 09/213300 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138704.pdf [firstpage_image] =>[orig_patent_app_number] => 09213300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213300
METHOD AND APPARATUS FAULT TOLERANT SHARED MEMORY Dec 14, 1998 Abandoned
Array ( [id] => 1471943 [patent_doc_number] => 06460119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Snoop blocking for cache coherency' [patent_app_type] => B1 [patent_app_number] => 09/210641 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3195 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460119.pdf [firstpage_image] =>[orig_patent_app_number] => 09210641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210641
Snoop blocking for cache coherency Dec 13, 1998 Issued
Array ( [id] => 6531841 [patent_doc_number] => 20020026561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'CACHE MANAGEMENT SYSTEM' [patent_app_type] => new [patent_app_number] => 09/209279 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2430 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026561.pdf [firstpage_image] =>[orig_patent_app_number] => 09209279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209279
Cache management system using cache control instructions for controlling the operation of cache Dec 10, 1998 Issued
Array ( [id] => 7634983 [patent_doc_number] => 06381683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method and system for destination-sensitive memory control and access in data processing systems' [patent_app_type] => B1 [patent_app_number] => 09/208522 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 31494 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381683.pdf [firstpage_image] =>[orig_patent_app_number] => 09208522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208522
Method and system for destination-sensitive memory control and access in data processing systems Dec 8, 1998 Issued
Array ( [id] => 4280934 [patent_doc_number] => 06260123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and system for memory control and access in data processing systems' [patent_app_type] => 1 [patent_app_number] => 9/208570 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13669 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260123.pdf [firstpage_image] =>[orig_patent_app_number] => 208570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208570
Method and system for memory control and access in data processing systems Dec 8, 1998 Issued
Array ( [id] => 1066738 [patent_doc_number] => 06851036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method and apparatus for controlling external devices through address translation buffer' [patent_app_type] => utility [patent_app_number] => 09/530787 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4379 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851036.pdf [firstpage_image] =>[orig_patent_app_number] => 09530787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/530787
Method and apparatus for controlling external devices through address translation buffer Nov 5, 1998 Issued
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