Search

Matthew C Graham

Examiner (ID: 12461, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3683, 3103, 3104, 2202, 3303, 3993
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1553763 [patent_doc_number] => 06347357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Enhanced DRAM with embedded registers' [patent_app_type] => B1 [patent_app_number] => 09/182994 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 14790 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347357.pdf [firstpage_image] =>[orig_patent_app_number] => 09182994 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182994
Enhanced DRAM with embedded registers Oct 29, 1998 Issued
Array ( [id] => 7095056 [patent_doc_number] => 20010034808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'CACHE MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM' [patent_app_type] => new [patent_app_number] => 09/182046 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5852 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034808.pdf [firstpage_image] =>[orig_patent_app_number] => 09182046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182046
CACHE MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM Oct 28, 1998 Abandoned
Array ( [id] => 1434045 [patent_doc_number] => 06341335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Information processing system for read ahead buffer memory equipped with register and memory controller' [patent_app_type] => B1 [patent_app_number] => 09/181676 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7464 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341335.pdf [firstpage_image] =>[orig_patent_app_number] => 09181676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181676
Information processing system for read ahead buffer memory equipped with register and memory controller Oct 28, 1998 Issued
09/171981 DATA PROCESSING SYSTEM Oct 28, 1998 Abandoned
Array ( [id] => 1297161 [patent_doc_number] => 06633966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'FIFO memory having reduced scale' [patent_app_type] => B1 [patent_app_number] => 09/176318 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633966.pdf [firstpage_image] =>[orig_patent_app_number] => 09176318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176318
FIFO memory having reduced scale Oct 21, 1998 Issued
Array ( [id] => 1406587 [patent_doc_number] => 06560674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Data cache system' [patent_app_type] => B1 [patent_app_number] => 09/172646 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 40 [patent_no_of_words] => 27693 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560674.pdf [firstpage_image] =>[orig_patent_app_number] => 09172646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172646
Data cache system Oct 13, 1998 Issued
09/173489 EVENT-ORIENTED MEMORY MANAGEMENT METHOD Oct 13, 1998 Abandoned
Array ( [id] => 1297046 [patent_doc_number] => 06633947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Memory expansion channel for propagation of control and request packets' [patent_app_type] => B1 [patent_app_number] => 09/154063 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 44 [patent_no_of_words] => 12121 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633947.pdf [firstpage_image] =>[orig_patent_app_number] => 09154063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154063
Memory expansion channel for propagation of control and request packets Sep 15, 1998 Issued
Array ( [id] => 4424533 [patent_doc_number] => 06266745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method and system in a distributed shared-memory data processing system for determining utilization of nodes by each executed thread' [patent_app_type] => 1 [patent_app_number] => 9/146391 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4050 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266745.pdf [firstpage_image] =>[orig_patent_app_number] => 146391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146391
Method and system in a distributed shared-memory data processing system for determining utilization of nodes by each executed thread Sep 3, 1998 Issued
Array ( [id] => 4424122 [patent_doc_number] => 06301643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Multi-environment data consistency' [patent_app_type] => 1 [patent_app_number] => 9/146413 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4489 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301643.pdf [firstpage_image] =>[orig_patent_app_number] => 146413 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146413
Multi-environment data consistency Sep 2, 1998 Issued
Array ( [id] => 1604498 [patent_doc_number] => 06434684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same' [patent_app_type] => B1 [patent_app_number] => 09/146946 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7653 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434684.pdf [firstpage_image] =>[orig_patent_app_number] => 09146946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146946
Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same Sep 2, 1998 Issued
Array ( [id] => 4422572 [patent_doc_number] => 06272612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Process for allocating memory in a multiprocessor data processing system' [patent_app_type] => 1 [patent_app_number] => 9/145642 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 9061 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 835 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272612.pdf [firstpage_image] =>[orig_patent_app_number] => 145642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145642
Process for allocating memory in a multiprocessor data processing system Sep 1, 1998 Issued
09/144861 CONTROL OF MEMORY ACCESS OPERATIONS Aug 31, 1998 Abandoned
Array ( [id] => 4294668 [patent_doc_number] => 06324622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => '6XX bus with exclusive intervention' [patent_app_type] => 1 [patent_app_number] => 9/138320 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2149 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324622.pdf [firstpage_image] =>[orig_patent_app_number] => 138320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138320
6XX bus with exclusive intervention Aug 23, 1998 Issued
Array ( [id] => 4298605 [patent_doc_number] => 06282616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Caching managing method for network and terminal for data retrieving' [patent_app_type] => 1 [patent_app_number] => 9/136069 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2273 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282616.pdf [firstpage_image] =>[orig_patent_app_number] => 136069 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136069
Caching managing method for network and terminal for data retrieving Aug 18, 1998 Issued
Array ( [id] => 4337119 [patent_doc_number] => 06249845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for supporting cache control instructions within a coherency granule' [patent_app_type] => 1 [patent_app_number] => 9/136329 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249845.pdf [firstpage_image] =>[orig_patent_app_number] => 136329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136329
Method for supporting cache control instructions within a coherency granule Aug 18, 1998 Issued
09/136213 METHOD AND APPARATUS TO CONTROL THE TEMPERATURE OF A COMPONENT Aug 17, 1998 Abandoned
Array ( [id] => 1456767 [patent_doc_number] => 06457106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Shared memory control system and shared memory control method' [patent_app_type] => B1 [patent_app_number] => 09/120239 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5116 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457106.pdf [firstpage_image] =>[orig_patent_app_number] => 09120239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120239
Shared memory control system and shared memory control method Jul 21, 1998 Issued
Array ( [id] => 4350830 [patent_doc_number] => 06334175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Switchable memory system and memory allocation method' [patent_app_type] => 1 [patent_app_number] => 9/120592 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4249 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334175.pdf [firstpage_image] =>[orig_patent_app_number] => 120592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120592
Switchable memory system and memory allocation method Jul 21, 1998 Issued
Array ( [id] => 4424537 [patent_doc_number] => 06266746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Control apparatus for random access memories' [patent_app_type] => 1 [patent_app_number] => 9/120277 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10507 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266746.pdf [firstpage_image] =>[orig_patent_app_number] => 120277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120277
Control apparatus for random access memories Jul 21, 1998 Issued
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