Search

Matthew C Graham

Examiner (ID: 12461, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3683, 3103, 3104, 2202, 3303, 3993
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4376489 [patent_doc_number] => 06219757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Cache flush operation for a stack-based microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/032396 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1896 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219757.pdf [firstpage_image] =>[orig_patent_app_number] => 032396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032396
Cache flush operation for a stack-based microprocessor Feb 26, 1998 Issued
Array ( [id] => 4424112 [patent_doc_number] => 06301641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method for reducing the frequency of cache misses in a computer' [patent_app_type] => 1 [patent_app_number] => 9/031696 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5201 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301641.pdf [firstpage_image] =>[orig_patent_app_number] => 031696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031696
Method for reducing the frequency of cache misses in a computer Feb 26, 1998 Issued
Array ( [id] => 4316362 [patent_doc_number] => 06199145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Configurable page closing method and apparatus for multi-port host bridges' [patent_app_type] => 1 [patent_app_number] => 9/032434 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199145.pdf [firstpage_image] =>[orig_patent_app_number] => 032434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032434
Configurable page closing method and apparatus for multi-port host bridges Feb 26, 1998 Issued
Array ( [id] => 4151461 [patent_doc_number] => 06148302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method, apparatus, system and computer program product for initializing a data structure at its first active use' [patent_app_type] => 1 [patent_app_number] => 9/031229 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7376 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148302.pdf [firstpage_image] =>[orig_patent_app_number] => 031229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031229
Method, apparatus, system and computer program product for initializing a data structure at its first active use Feb 25, 1998 Issued
Array ( [id] => 6878326 [patent_doc_number] => 20010002481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'DATA ACCESS UNIT AND METHOD THEREFOR' [patent_app_type] => new-utility [patent_app_number] => 09/030829 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 16511 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002481.pdf [firstpage_image] =>[orig_patent_app_number] => 09030829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030829
DATA ACCESS UNIT AND METHOD THEREFOR Feb 25, 1998 Abandoned
Array ( [id] => 4257028 [patent_doc_number] => 06081878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/030697 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 13133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081878.pdf [firstpage_image] =>[orig_patent_app_number] => 030697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030697
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices Feb 24, 1998 Issued
Array ( [id] => 4422529 [patent_doc_number] => 06173374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'System and method for peer-to-peer accelerated I/O shipping between host bus adapters in clustered computer network' [patent_app_type] => 1 [patent_app_number] => 9/022350 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7879 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173374.pdf [firstpage_image] =>[orig_patent_app_number] => 022350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022350
System and method for peer-to-peer accelerated I/O shipping between host bus adapters in clustered computer network Feb 10, 1998 Issued
Array ( [id] => 4422659 [patent_doc_number] => 06173384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of searching for a data element in a data structure' [patent_app_type] => 1 [patent_app_number] => 9/021970 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4228 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173384.pdf [firstpage_image] =>[orig_patent_app_number] => 021970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021970
Method of searching for a data element in a data structure Feb 10, 1998 Issued
Array ( [id] => 757600 [patent_doc_number] => 07024512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Compression store free-space management' [patent_app_type] => utility [patent_app_number] => 09/021333 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7250 [patent_no_of_claims] => 97 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024512.pdf [firstpage_image] =>[orig_patent_app_number] => 09021333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021333
Compression store free-space management Feb 9, 1998 Issued
Array ( [id] => 4292302 [patent_doc_number] => 06247103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Host storage management control of outboard data movement using push-pull operations' [patent_app_type] => 1 [patent_app_number] => 9/003532 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3626 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247103.pdf [firstpage_image] =>[orig_patent_app_number] => 003532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003532
Host storage management control of outboard data movement using push-pull operations Jan 5, 1998 Issued
Array ( [id] => 1466246 [patent_doc_number] => 06393537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Host storage management control of outboard data movement' [patent_app_type] => B1 [patent_app_number] => 09/003544 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3402 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393537.pdf [firstpage_image] =>[orig_patent_app_number] => 09003544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003544
Host storage management control of outboard data movement Jan 5, 1998 Issued
Array ( [id] => 4349737 [patent_doc_number] => 06321310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Memory architecture for a computer system' [patent_app_type] => 1 [patent_app_number] => 9/003526 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 13175 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321310.pdf [firstpage_image] =>[orig_patent_app_number] => 003526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003526
Memory architecture for a computer system Jan 5, 1998 Issued
Array ( [id] => 1431435 [patent_doc_number] => 06519686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Information streaming in a multi-process system using shared memory' [patent_app_type] => B2 [patent_app_number] => 09/002770 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4675 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519686.pdf [firstpage_image] =>[orig_patent_app_number] => 09002770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002770
Information streaming in a multi-process system using shared memory Jan 4, 1998 Issued
Array ( [id] => 4426914 [patent_doc_number] => 06195735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Prefetch circuity for prefetching variable size data' [patent_app_type] => 1 [patent_app_number] => 8/999091 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 11168 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195735.pdf [firstpage_image] =>[orig_patent_app_number] => 999091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999091
Prefetch circuity for prefetching variable size data Dec 28, 1997 Issued
Array ( [id] => 4147562 [patent_doc_number] => 06128708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method for testing and mitigating shared memory contention in multi-processor systems' [patent_app_type] => 1 [patent_app_number] => 8/998218 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3640 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128708.pdf [firstpage_image] =>[orig_patent_app_number] => 998218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998218
Method for testing and mitigating shared memory contention in multi-processor systems Dec 23, 1997 Issued
Array ( [id] => 4290214 [patent_doc_number] => 06308241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'On-chip cache file register for minimizing CPU idle cycles during cache refills' [patent_app_type] => 1 [patent_app_number] => 8/995820 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1850 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308241.pdf [firstpage_image] =>[orig_patent_app_number] => 995820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995820
On-chip cache file register for minimizing CPU idle cycles during cache refills Dec 21, 1997 Issued
Array ( [id] => 4310138 [patent_doc_number] => 06212602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Cache tag caching' [patent_app_type] => 1 [patent_app_number] => 8/992305 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6384 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212602.pdf [firstpage_image] =>[orig_patent_app_number] => 992305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992305
Cache tag caching Dec 16, 1997 Issued
Array ( [id] => 4199080 [patent_doc_number] => 06038642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method and system for assigning cache memory utilization within a symmetric multiprocessor data-processing system' [patent_app_type] => 1 [patent_app_number] => 8/992134 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3001 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038642.pdf [firstpage_image] =>[orig_patent_app_number] => 992134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992134
Method and system for assigning cache memory utilization within a symmetric multiprocessor data-processing system Dec 16, 1997 Issued
Array ( [id] => 4317713 [patent_doc_number] => 06185658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Cache with enhanced victim selection using the coherency states of cache lines' [patent_app_type] => 1 [patent_app_number] => 8/992137 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5311 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185658.pdf [firstpage_image] =>[orig_patent_app_number] => 992137 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992137
Cache with enhanced victim selection using the coherency states of cache lines Dec 16, 1997 Issued
Array ( [id] => 4202445 [patent_doc_number] => 06094710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system' [patent_app_type] => 1 [patent_app_number] => 8/992786 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2269 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094710.pdf [firstpage_image] =>[orig_patent_app_number] => 992786 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992786
Method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system Dec 16, 1997 Issued
Menu