Search

Matthew C Graham

Examiner (ID: 12461, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3683, 3103, 3104, 2202, 3303, 3993
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4224002 [patent_doc_number] => 06079003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache' [patent_app_type] => 1 [patent_app_number] => 8/974972 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13882 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079003.pdf [firstpage_image] =>[orig_patent_app_number] => 974972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974972
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache Nov 19, 1997 Issued
Array ( [id] => 7638609 [patent_doc_number] => 06397312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Memory subsystem operated in synchronism with a clock' [patent_app_type] => B1 [patent_app_number] => 08/970086 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9054 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397312.pdf [firstpage_image] =>[orig_patent_app_number] => 08970086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970086
Memory subsystem operated in synchronism with a clock Nov 12, 1997 Issued
Array ( [id] => 4230123 [patent_doc_number] => 06111813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Apparatus and method for tracking dynamic sense amplifier enable signals with memory array accessing signals in a synchronous RAM' [patent_app_type] => 1 [patent_app_number] => 8/940384 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3248 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111813.pdf [firstpage_image] =>[orig_patent_app_number] => 940384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940384
Apparatus and method for tracking dynamic sense amplifier enable signals with memory array accessing signals in a synchronous RAM Sep 29, 1997 Issued
Array ( [id] => 7634992 [patent_doc_number] => 06381674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method and apparatus for providing centralized intelligent cache between multiple data controlling elements' [patent_app_type] => B2 [patent_app_number] => 08/941770 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11123 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381674.pdf [firstpage_image] =>[orig_patent_app_number] => 08941770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941770
Method and apparatus for providing centralized intelligent cache between multiple data controlling elements Sep 29, 1997 Issued
Array ( [id] => 1592329 [patent_doc_number] => 06360303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Partitioning memory shared by multiple processors of a distributed processing system' [patent_app_type] => B1 [patent_app_number] => 08/940340 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3524 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360303.pdf [firstpage_image] =>[orig_patent_app_number] => 08940340 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940340
Partitioning memory shared by multiple processors of a distributed processing system Sep 29, 1997 Issued
08/936302 OPTIMIZING SCHEDULER FOR READ/WRITE OPERATIONS IN A DISK FILE SYSTEM Sep 23, 1997 Abandoned
Array ( [id] => 4237358 [patent_doc_number] => 06112285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support' [patent_app_type] => 1 [patent_app_number] => 8/935819 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 13799 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112285.pdf [firstpage_image] =>[orig_patent_app_number] => 935819 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935819
Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support Sep 22, 1997 Issued
Array ( [id] => 4373824 [patent_doc_number] => 06202137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method and apparatus of arbitrating requests to a multi-banked memory using bank selects' [patent_app_type] => 1 [patent_app_number] => 8/932521 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7187 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202137.pdf [firstpage_image] =>[orig_patent_app_number] => 932521 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932521
Method and apparatus of arbitrating requests to a multi-banked memory using bank selects Sep 17, 1997 Issued
Array ( [id] => 4269079 [patent_doc_number] => 06138209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/924272 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9703 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138209.pdf [firstpage_image] =>[orig_patent_app_number] => 924272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924272
Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof Sep 4, 1997 Issued
Array ( [id] => 4138868 [patent_doc_number] => 06073220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Apparatus and method for providing a transparent disk drive back-up' [patent_app_type] => 1 [patent_app_number] => 8/922403 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073220.pdf [firstpage_image] =>[orig_patent_app_number] => 922403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922403
Apparatus and method for providing a transparent disk drive back-up Sep 2, 1997 Issued
Array ( [id] => 3967496 [patent_doc_number] => 05983333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'High speed module address generator' [patent_app_type] => 1 [patent_app_number] => 8/919054 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2974 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983333.pdf [firstpage_image] =>[orig_patent_app_number] => 919054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919054
High speed module address generator Aug 26, 1997 Issued
Array ( [id] => 4099939 [patent_doc_number] => 06055610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations' [patent_app_type] => 1 [patent_app_number] => 8/918209 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7188 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055610.pdf [firstpage_image] =>[orig_patent_app_number] => 918209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918209
Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations Aug 24, 1997 Issued
Array ( [id] => 4270336 [patent_doc_number] => 06223266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'System and method for interfacing an input/output system memory to a host computer system memory' [patent_app_type] => 1 [patent_app_number] => 8/914960 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223266.pdf [firstpage_image] =>[orig_patent_app_number] => 914960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914960
System and method for interfacing an input/output system memory to a host computer system memory Aug 19, 1997 Issued
Array ( [id] => 4310059 [patent_doc_number] => 06212597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like' [patent_app_type] => 1 [patent_app_number] => 8/901502 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5771 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212597.pdf [firstpage_image] =>[orig_patent_app_number] => 901502 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901502
Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like Jul 27, 1997 Issued
08/900764 CACHING UTILITY Jul 24, 1997 Abandoned
Array ( [id] => 4254999 [patent_doc_number] => 06119202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus to interleave level 1 data cache line fill data between system bus and level 2 data cache for improved processor performance' [patent_app_type] => 1 [patent_app_number] => 8/899850 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3947 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119202.pdf [firstpage_image] =>[orig_patent_app_number] => 899850 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899850
Method and apparatus to interleave level 1 data cache line fill data between system bus and level 2 data cache for improved processor performance Jul 23, 1997 Issued
Array ( [id] => 4152559 [patent_doc_number] => 06035427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Convolutional interleaver and method for generating memory address therefor' [patent_app_type] => 1 [patent_app_number] => 8/886514 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5031 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035427.pdf [firstpage_image] =>[orig_patent_app_number] => 886514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886514
Convolutional interleaver and method for generating memory address therefor Jun 30, 1997 Issued
08/884604 METHOD OF OPERATING A RAID DISK ARRAY IN A HARDWARE - ADDRESS- INDEPENDENT MANNER , AND DISK STORAGE SYSTEM WHICH PERFORMS SUCH METHOD Jun 26, 1997 Abandoned
Array ( [id] => 4256952 [patent_doc_number] => 06081873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'In-line bank conflict detection and resolution in a multi-ported non-blocking cache' [patent_app_type] => 1 [patent_app_number] => 8/881065 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8775 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081873.pdf [firstpage_image] =>[orig_patent_app_number] => 881065 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881065
In-line bank conflict detection and resolution in a multi-ported non-blocking cache Jun 24, 1997 Issued
Array ( [id] => 4259764 [patent_doc_number] => 06092152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for stack-caching method frames' [patent_app_type] => 1 [patent_app_number] => 8/880466 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4058 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092152.pdf [firstpage_image] =>[orig_patent_app_number] => 880466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880466
Method for stack-caching method frames Jun 22, 1997 Issued
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