Matthew C Graham

Array ( [id] => 4161402 [patent_doc_number] => 06061822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'System and method for providing a fast and efficient comparison of cyclic redundancy check (CRC/checks sum) values of two mirrored disks' [patent_app_type] => 1 [patent_app_number] => 8/880350 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6364 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061822.pdf [firstpage_image] =>[orig_patent_app_number] => 880350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932819 [patent_doc_number] => 06003114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Caching system and method providing aggressive prefetch' [patent_app_type] => 1 [patent_app_number] => 8/877700 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003114.pdf [firstpage_image] =>[orig_patent_app_number] => 877700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126697 [patent_doc_number] => 06058454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method and system for automatically configuring redundant arrays of disk memory devices' [patent_app_type] => 1 [patent_app_number] => 8/936228 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9658 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058454.pdf [firstpage_image] =>[orig_patent_app_number] => 936228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114564 [patent_doc_number] => 06049856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'System for simultaneously accessing two portions of a shared memory' [patent_app_type] => 1 [patent_app_number] => 8/862880 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 21 [patent_no_of_words] => 13399 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049856.pdf [firstpage_image] =>[orig_patent_app_number] => 862880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4160633 [patent_doc_number] => 06061774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Limited virtual address aliasing and fast context switching with multi-set virtual cache without backmaps' [patent_app_type] => 1 [patent_app_number] => 8/863084 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2214 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061774.pdf [firstpage_image] =>[orig_patent_app_number] => 863084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3961383 [patent_doc_number] => 05974497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Computer with cache-line buffers for storing prefetched data for a misaligned memory access' [patent_app_type] => 1 [patent_app_number] => 8/861778 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974497.pdf [firstpage_image] =>[orig_patent_app_number] => 861778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152716 [patent_doc_number] => 06148385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'High speed digital electronic memory having a read and write in one cycle' [patent_app_type] => 1 [patent_app_number] => 8/861273 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3583 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148385.pdf [firstpage_image] =>[orig_patent_app_number] => 861273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971062 [patent_doc_number] => 06000009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus for allocation of disk memory space for compressed data records' [patent_app_type] => 1 [patent_app_number] => 8/851109 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3308 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000009.pdf [firstpage_image] =>[orig_patent_app_number] => 851109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970473 [patent_doc_number] => 05991851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control' [patent_app_type] => 1 [patent_app_number] => 8/850802 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6912 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991851.pdf [firstpage_image] =>[orig_patent_app_number] => 850802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4006897 [patent_doc_number] => 05960457 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Cache coherency test system and methodology for testing cache operation in the presence of an external snoop' [patent_app_type] => 1 [patent_app_number] => 8/846651 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4469 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960457.pdf [firstpage_image] =>[orig_patent_app_number] => 846651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4071726 [patent_doc_number] => 05933857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Accessing multiple independent microkernels existing in a globally shared memory system' [patent_app_type] => 1 [patent_app_number] => 8/845306 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4358 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933857.pdf [firstpage_image] =>[orig_patent_app_number] => 845306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4084094 [patent_doc_number] => 06009426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of managing a shared memory using read and write locks' [patent_app_type] => 1 [patent_app_number] => 8/844635 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4975 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 978 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009426.pdf [firstpage_image] =>[orig_patent_app_number] => 844635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4033800 [patent_doc_number] => 05963983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for dynamically creating conversion tables to access a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/842554 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11863 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963983.pdf [firstpage_image] =>[orig_patent_app_number] => 842554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4052200 [patent_doc_number] => 05943686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Multiple cache directories for non-arbitration concurrent accessing of a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/834492 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5993 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943686.pdf [firstpage_image] =>[orig_patent_app_number] => 834492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057420 [patent_doc_number] => 05996051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array' [patent_app_type] => 1 [patent_app_number] => 8/837119 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6617 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996051.pdf [firstpage_image] =>[orig_patent_app_number] => 837119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970167 [patent_doc_number] => 05958045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/831194 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9615 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958045.pdf [firstpage_image] =>[orig_patent_app_number] => 831194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4030418 [patent_doc_number] => 05907716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Fifo buffer capable of partially erasing data set held therein' [patent_app_type] => 1 [patent_app_number] => 8/829953 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5038 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907716.pdf [firstpage_image] =>[orig_patent_app_number] => 829953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960423 [patent_doc_number] => 05930829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Dynamic memory allocation for a random access memory employing separately stored space allocation information using a tree structure' [patent_app_type] => 1 [patent_app_number] => 8/829391 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3542 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930829.pdf [firstpage_image] =>[orig_patent_app_number] => 829391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3955354 [patent_doc_number] => 05940865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Apparatus and method for accessing plural storage devices in predetermined order by slot allocation' [patent_app_type] => 1 [patent_app_number] => 8/828563 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940865.pdf [firstpage_image] =>[orig_patent_app_number] => 828563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040616 [patent_doc_number] => 05926826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Flash memory erasable programmable ROM that has uniform erasing and a replaceable writing start mark, flag, or pointer for use in blank, free, or empty blocks' [patent_app_type] => 1 [patent_app_number] => 8/825394 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4279 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926826.pdf [firstpage_image] =>[orig_patent_app_number] => 825394 [rel_patent_id] =>[rel_patent_doc_number] =>)