Search

Matthew C Graham

Examiner (ID: 12461, Phone: (571)272-7116 , Office: P/3993 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3683, 3103, 3104, 2202, 3303, 3993
Total Applications
2166
Issued Applications
1848
Pending Applications
68
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4084976 [patent_doc_number] => 06009482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method and apparatus for enabling cache streaming' [patent_app_type] => 1 [patent_app_number] => 8/829554 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3017 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009482.pdf [firstpage_image] =>[orig_patent_app_number] => 829554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829554
Method and apparatus for enabling cache streaming Mar 27, 1997 Issued
Array ( [id] => 3997067 [patent_doc_number] => 05961621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system' [patent_app_type] => 1 [patent_app_number] => 8/827540 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3464 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961621.pdf [firstpage_image] =>[orig_patent_app_number] => 827540 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827540
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system Mar 27, 1997 Issued
Array ( [id] => 4057678 [patent_doc_number] => 05996068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and apparatus for renaming registers corresponding to multiple thread identifications' [patent_app_type] => 1 [patent_app_number] => 8/824599 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2501 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996068.pdf [firstpage_image] =>[orig_patent_app_number] => 824599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824599
Method and apparatus for renaming registers corresponding to multiple thread identifications Mar 25, 1997 Issued
Array ( [id] => 4349709 [patent_doc_number] => 06321308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method and apparatus for managing access requests from a plurality of devices using dual level queue locking scheme and a doubly-linked circular queue' [patent_app_type] => 1 [patent_app_number] => 8/822971 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4947 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321308.pdf [firstpage_image] =>[orig_patent_app_number] => 822971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822971
Method and apparatus for managing access requests from a plurality of devices using dual level queue locking scheme and a doubly-linked circular queue Mar 20, 1997 Issued
Array ( [id] => 4011168 [patent_doc_number] => 05920896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Reducing operating system start-up/boot time through disk block relocation' [patent_app_type] => 1 [patent_app_number] => 8/822640 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4257 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920896.pdf [firstpage_image] =>[orig_patent_app_number] => 822640 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822640
Reducing operating system start-up/boot time through disk block relocation Mar 20, 1997 Issued
Array ( [id] => 4100015 [patent_doc_number] => 06055615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Pipeline memory access using DRAM with multiple independent banks' [patent_app_type] => 1 [patent_app_number] => 8/792134 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 56 [patent_no_of_words] => 9491 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055615.pdf [firstpage_image] =>[orig_patent_app_number] => 792134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792134
Pipeline memory access using DRAM with multiple independent banks Jan 30, 1997 Issued
Array ( [id] => 4060360 [patent_doc_number] => 05913226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Snoop cache memory control system and method' [patent_app_type] => 1 [patent_app_number] => 8/779154 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 12514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913226.pdf [firstpage_image] =>[orig_patent_app_number] => 779154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779154
Snoop cache memory control system and method Jan 2, 1997 Issued
Array ( [id] => 4240100 [patent_doc_number] => 06012126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'System and method for caching objects of non-uniform size using multiple LRU stacks partitions into a range of sizes' [patent_app_type] => 1 [patent_app_number] => 8/741412 [patent_app_country] => US [patent_app_date] => 1996-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4143 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012126.pdf [firstpage_image] =>[orig_patent_app_number] => 741412 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/741412
System and method for caching objects of non-uniform size using multiple LRU stacks partitions into a range of sizes Oct 28, 1996 Issued
Array ( [id] => 4085309 [patent_doc_number] => 06009503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Cache memory indexing using virtual, primary and secondary color indexes' [patent_app_type] => 1 [patent_app_number] => 8/732352 [patent_app_country] => US [patent_app_date] => 1996-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009503.pdf [firstpage_image] =>[orig_patent_app_number] => 732352 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/732352
Cache memory indexing using virtual, primary and secondary color indexes Oct 28, 1996 Issued
Array ( [id] => 3978335 [patent_doc_number] => 05937437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method and apparatus for monitoring address translation performance' [patent_app_type] => 1 [patent_app_number] => 8/738748 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4246 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937437.pdf [firstpage_image] =>[orig_patent_app_number] => 738748 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738748
Method and apparatus for monitoring address translation performance Oct 27, 1996 Issued
Array ( [id] => 4026963 [patent_doc_number] => 05890206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method of writing sequential data to a disc memory system having a fixed block architecture' [patent_app_type] => 1 [patent_app_number] => 8/727092 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2412 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890206.pdf [firstpage_image] =>[orig_patent_app_number] => 727092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727092
Method of writing sequential data to a disc memory system having a fixed block architecture Oct 6, 1996 Issued
Menu