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Matthew Chabak

Examiner (ID: 19229)

Most Active Art Unit
5333
Art Unit(s)
5332, 5333
Total Applications
505
Issued Applications
0
Pending Applications
505
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10022298 [patent_doc_number] => 09064793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Encapsulated phase change cell structures and methods' [patent_app_type] => utility [patent_app_number] => 14/184142 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/184142
Encapsulated phase change cell structures and methods Feb 18, 2014 Issued
Array ( [id] => 10508408 [patent_doc_number] => 09236284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Cooled tape frame lift and low contact shadow ring for plasma heat isolation' [patent_app_type] => utility [patent_app_number] => 14/169356 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 15242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169356 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/169356
Cooled tape frame lift and low contact shadow ring for plasma heat isolation Jan 30, 2014 Issued
Array ( [id] => 10138397 [patent_doc_number] => 09171719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Method of defining poly-silicon growth direction' [patent_app_type] => utility [patent_app_number] => 14/348887 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2126 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14348887 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/348887
Method of defining poly-silicon growth direction Jan 22, 2014 Issued
Array ( [id] => 9474300 [patent_doc_number] => 20140131763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SELF-BOOTSTRAPPING FIELD EFFECT DIODE STRUCTURES AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/158599 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5074 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158599 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158599
Self-bootstrapping field effect diode structures and methods Jan 16, 2014 Issued
Array ( [id] => 9474432 [patent_doc_number] => 20140131896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'Exposing Connectors in Packages Through Selective Treatment' [patent_app_type] => utility [patent_app_number] => 14/157617 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/157617
Exposing connectors in packages through selective treatment Jan 16, 2014 Issued
Array ( [id] => 10016165 [patent_doc_number] => 09059186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Embedded semiconductor die package and method of making the same using metal frame carrier' [patent_app_type] => utility [patent_app_number] => 14/154049 [patent_app_country] => US [patent_app_date] => 2014-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 6243 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14154049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/154049
Embedded semiconductor die package and method of making the same using metal frame carrier Jan 12, 2014 Issued
Array ( [id] => 10315133 [patent_doc_number] => 20150200136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD FOR FORMING CONTACT AND METHOD FOR ETCHING CONTINUOUS RECESS' [patent_app_type] => utility [patent_app_number] => 14/152115 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152115 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152115
Semiconductor device, method for forming contact and method for etching continuous recess Jan 9, 2014 Issued
Array ( [id] => 10106894 [patent_doc_number] => 09142676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Semiconductor liner of semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/144219 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144219
Semiconductor liner of semiconductor device Dec 29, 2013 Issued
Array ( [id] => 10073668 [patent_doc_number] => 09112033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Source/drain structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/144198 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144198
Source/drain structure of semiconductor device Dec 29, 2013 Issued
Array ( [id] => 9432955 [patent_doc_number] => 20140110861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support' [patent_app_type] => utility [patent_app_number] => 14/143891 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5798 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143891
Semiconductor device and method of making TSV interconnect structures using encapsulant for structural support Dec 29, 2013 Issued
Array ( [id] => 10042072 [patent_doc_number] => 09082786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Method of fabricating a self-aligning damascene memory structure' [patent_app_type] => utility [patent_app_number] => 14/140468 [patent_app_country] => US [patent_app_date] => 2013-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140468
Method of fabricating a self-aligning damascene memory structure Dec 23, 2013 Issued
Array ( [id] => 9634962 [patent_doc_number] => 20140213071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'LASER ANNEALING METHOD AND DEVICE' [patent_app_type] => utility [patent_app_number] => 14/138273 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9935 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138273 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138273
Laser annealing method and device Dec 22, 2013 Issued
Array ( [id] => 10189580 [patent_doc_number] => 09219009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Method of integrated circuit fabrication' [patent_app_type] => utility [patent_app_number] => 14/136823 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136823 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136823
Method of integrated circuit fabrication Dec 19, 2013 Issued
Array ( [id] => 10286012 [patent_doc_number] => 20150171010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'SELF-ALIGNED VIA AND PLUG PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 14/133385 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133385
Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects Dec 17, 2013 Issued
Array ( [id] => 10080053 [patent_doc_number] => 09117908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor products' [patent_app_type] => utility [patent_app_number] => 14/107279 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6954 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107279
Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor products Dec 15, 2013 Issued
Array ( [id] => 10286224 [patent_doc_number] => 20150171223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'METHODS FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/107935 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2797 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107935 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107935
Methods for fabricating semiconductor device Dec 15, 2013 Issued
Array ( [id] => 9875926 [patent_doc_number] => 08963197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Light emitting diode package' [patent_app_type] => utility [patent_app_number] => 14/107193 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4230 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107193 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107193
Light emitting diode package Dec 15, 2013 Issued
Array ( [id] => 9875195 [patent_doc_number] => 08962461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'GaN HEMTs and GaN diodes' [patent_app_type] => utility [patent_app_number] => 14/108042 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4954 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108042 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/108042
GaN HEMTs and GaN diodes Dec 15, 2013 Issued
Array ( [id] => 9958629 [patent_doc_number] => 09006840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Semiconductor device and semiconductor system including the same' [patent_app_type] => utility [patent_app_number] => 14/107958 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107958 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107958
Semiconductor device and semiconductor system including the same Dec 15, 2013 Issued
Array ( [id] => 9928474 [patent_doc_number] => 20150076666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA' [patent_app_type] => utility [patent_app_number] => 14/107214 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2860 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107214
SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA Dec 15, 2013 Abandoned
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