Search

Matthew Chabak

Examiner (ID: 19229)

Most Active Art Unit
5333
Art Unit(s)
5332, 5333
Total Applications
505
Issued Applications
0
Pending Applications
505
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10079955 [patent_doc_number] => 09117808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Semiconductor packages and methods of packaging semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/257013 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 4823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257013 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/257013
Semiconductor packages and methods of packaging semiconductor devices Apr 20, 2014 Issued
Array ( [id] => 9951060 [patent_doc_number] => 08999846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Elongated via structures' [patent_app_type] => utility [patent_app_number] => 14/255037 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3827 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255037 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255037
Elongated via structures Apr 16, 2014 Issued
Array ( [id] => 10409924 [patent_doc_number] => 20150294933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'PATTERN BETWEEN PATTERN FOR LOW PROFILE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/253798 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3498 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/253798
Pattern between pattern for low profile substrate Apr 14, 2014 Issued
Array ( [id] => 10409897 [patent_doc_number] => 20150294905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/249407 [patent_app_country] => US [patent_app_date] => 2014-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9955 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14249407 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/249407
Semiconductor arrangement and formation thereof Apr 9, 2014 Issued
Array ( [id] => 10053614 [patent_doc_number] => 09093500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Methods of forming semiconductor device using bowing control layer' [patent_app_type] => utility [patent_app_number] => 14/247635 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 54 [patent_no_of_words] => 12361 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247635 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247635
Methods of forming semiconductor device using bowing control layer Apr 7, 2014 Issued
Array ( [id] => 10919816 [patent_doc_number] => 20140322835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'METHOD OF MANUFACTURING LIQUID DISCHARGE HEAD' [patent_app_type] => utility [patent_app_number] => 14/247445 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3232 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247445 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247445
Method of manufacturing liquid discharge head Apr 7, 2014 Issued
Array ( [id] => 10073660 [patent_doc_number] => 09112025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'LDMOS device and fabrication method' [patent_app_type] => utility [patent_app_number] => 14/247496 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247496 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247496
LDMOS device and fabrication method Apr 7, 2014 Issued
Array ( [id] => 10022243 [patent_doc_number] => 09064736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Method of manufacturing three dimensional semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/248003 [patent_app_country] => US [patent_app_date] => 2014-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14248003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/248003
Method of manufacturing three dimensional semiconductor memory device Apr 7, 2014 Issued
Array ( [id] => 9951075 [patent_doc_number] => 08999862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-07 [patent_title] => 'Methods of fabricating nano-scale structures and nano-scale structures fabricated thereby' [patent_app_type] => utility [patent_app_number] => 14/247063 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247063
Methods of fabricating nano-scale structures and nano-scale structures fabricated thereby Apr 6, 2014 Issued
Array ( [id] => 9909698 [patent_doc_number] => 20150064899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH-SILICON VIA (TSV) STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/247234 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10018 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247234 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247234
Method of fabricating semiconductor devices having through-silicon via (TSV) structures Apr 6, 2014 Issued
Array ( [id] => 9785801 [patent_doc_number] => 20140302621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/246249 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/246249
Semiconductor device and manufacturing method therefor Apr 6, 2014 Issued
Array ( [id] => 10042003 [patent_doc_number] => 09082716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/245304 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3676 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245304 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245304
Method of manufacturing semiconductor device Apr 3, 2014 Issued
Array ( [id] => 10184946 [patent_doc_number] => 09214630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'Method of making a multicomponent film' [patent_app_type] => utility [patent_app_number] => 14/245403 [patent_app_country] => US [patent_app_date] => 2014-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14245403 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/245403
Method of making a multicomponent film Apr 3, 2014 Issued
Array ( [id] => 10590515 [patent_doc_number] => 09312135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Method of manufacturing semiconductor devices including generating and annealing radiation-induced crystal defects' [patent_app_type] => utility [patent_app_number] => 14/219706 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3586 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219706 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219706
Method of manufacturing semiconductor devices including generating and annealing radiation-induced crystal defects Mar 18, 2014 Issued
Array ( [id] => 10377888 [patent_doc_number] => 20150262895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Pillar Structure having Cavities' [patent_app_type] => utility [patent_app_number] => 14/216656 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216656 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216656
Pillar structure having cavities Mar 16, 2014 Issued
Array ( [id] => 10508569 [patent_doc_number] => 09236446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Barc-assisted process for planar recessing or removing of variable-height layers' [patent_app_type] => utility [patent_app_number] => 14/208697 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 6859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14208697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/208697
Barc-assisted process for planar recessing or removing of variable-height layers Mar 12, 2014 Issued
Array ( [id] => 10518708 [patent_doc_number] => 09245763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Mechanisms for forming patterns using multiple lithography processes' [patent_app_type] => utility [patent_app_number] => 14/210032 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 68 [patent_no_of_words] => 9574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14210032 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/210032
Mechanisms for forming patterns using multiple lithography processes Mar 12, 2014 Issued
Array ( [id] => 10188503 [patent_doc_number] => 09217917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Three-direction alignment mark' [patent_app_type] => utility [patent_app_number] => 14/192225 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192225
Three-direction alignment mark Feb 26, 2014 Issued
Array ( [id] => 9557949 [patent_doc_number] => 20140175662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'POWER LAYOUT FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/189181 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189181 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189181
Power layout for integrated circuits Feb 24, 2014 Issued
Array ( [id] => 10358758 [patent_doc_number] => 20150243763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'PERFORMANCE BOOST BY SILICON EPITAXY' [patent_app_type] => utility [patent_app_number] => 14/187850 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7976 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187850
Performance boost by silicon epitaxy Feb 23, 2014 Issued
Menu