Search

Matthew D. Sandifer

Examiner (ID: 13275, Phone: (571)270-5175 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2151, 2193, 2182, 2183
Total Applications
831
Issued Applications
670
Pending Applications
43
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20408751 [patent_doc_number] => 20250377860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => CIRCUIT FOR EFFICIENTLY PERFORMING OPERATIONS ON INPUT DATA TO COMPUTE AN INTERPRETABLE AND DIFFERENTIABLE FUNCTION [patent_app_type] => utility [patent_app_number] => 19/232245 [patent_app_country] => US [patent_app_date] => 2025-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19232245 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/232245
CIRCUIT FOR EFFICIENTLY PERFORMING OPERATIONS ON INPUT DATA TO COMPUTE AN INTERPRETABLE AND DIFFERENTIABLE FUNCTION Jun 8, 2025 Pending
Array ( [id] => 20101643 [patent_doc_number] => 20250231579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => METHODS FOR DESIGNING HIGH FREEDOM PARAMETERIZED FREQUENCY-MODULATED CODED WAVEFORM [patent_app_type] => utility [patent_app_number] => 19/097839 [patent_app_country] => US [patent_app_date] => 2025-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19097839 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/097839
Methods for designing high freedom parameterized frequency-modulated coded waveform Mar 31, 2025 Issued
Array ( [id] => 20350969 [patent_doc_number] => 20250347821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => AEROELECTROMAGNETIC DATA INVERSION METHOD AND SYSTEM BASED ON APPROXIMATE JACOBIAN MATRIX [patent_app_type] => utility [patent_app_number] => 19/046863 [patent_app_country] => US [patent_app_date] => 2025-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19046863 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/046863
AEROELECTROMAGNETIC DATA INVERSION METHOD AND SYSTEM BASED ON APPROXIMATE JACOBIAN MATRIX Feb 5, 2025 Abandoned
Array ( [id] => 19963334 [patent_doc_number] => 12332835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-17 [patent_title] => Calculator capable of outputting results based on handwritten formulas [patent_app_type] => utility [patent_app_number] => 19/005765 [patent_app_country] => US [patent_app_date] => 2024-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1225 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19005765 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/005765
Calculator capable of outputting results based on handwritten formulas Dec 29, 2024 Issued
Array ( [id] => 20228602 [patent_doc_number] => 12417255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Collective communication optimization method for global high-degree vertices, and application [patent_app_type] => utility [patent_app_number] => 18/901245 [patent_app_country] => US [patent_app_date] => 2024-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2279 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18901245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/901245
Collective communication optimization method for global high-degree vertices, and application Sep 29, 2024 Issued
Array ( [id] => 19864504 [patent_doc_number] => 20250103290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => PROCESSING DEVICE USING DYNAMIC BIT SHIFT [patent_app_type] => utility [patent_app_number] => 18/892280 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18892280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/892280
Processing device using dynamic bit shift Sep 19, 2024 Issued
Array ( [id] => 19963762 [patent_doc_number] => 12333271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Processing device using heterogeneous format input [patent_app_type] => utility [patent_app_number] => 18/892274 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 22239 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18892274 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/892274
Processing device using heterogeneous format input Sep 19, 2024 Issued
Array ( [id] => 20610125 [patent_doc_number] => 12585727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Bit matrix multiplication [patent_app_type] => utility [patent_app_number] => 18/754719 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 14756 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754719 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754719
Bit matrix multiplication Jun 25, 2024 Issued
Array ( [id] => 19971570 [patent_doc_number] => 12340185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Processing core with data associative adaptive rounding [patent_app_type] => utility [patent_app_number] => 18/746561 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3877 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746561
Processing core with data associative adaptive rounding Jun 17, 2024 Issued
Array ( [id] => 19482161 [patent_doc_number] => 20240330203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 18/739768 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739768
Method and apparatus for implied bit handling in floating point multiplication Jun 10, 2024 Issued
Array ( [id] => 19334252 [patent_doc_number] => 20240248682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Multiple Mode Arithmetic Circuit [patent_app_type] => utility [patent_app_number] => 18/603800 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603800
Multiple mode arithmetic circuit Mar 12, 2024 Issued
Array ( [id] => 20440267 [patent_doc_number] => 12511103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Combinatorial logic circuits with feedback [patent_app_type] => utility [patent_app_number] => 18/602936 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602936 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602936
Combinatorial logic circuits with feedback Mar 11, 2024 Issued
Array ( [id] => 20481696 [patent_doc_number] => 12530171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Systems and methods employing unique device for generating random signals and metering and addressing, e.g., unusual deviations in said random signals [patent_app_type] => utility [patent_app_number] => 18/587519 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 45 [patent_no_of_words] => 37336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587519
Systems and methods employing unique device for generating random signals and metering and addressing, e.g., unusual deviations in said random signals Feb 25, 2024 Issued
Array ( [id] => 20550601 [patent_doc_number] => 12561395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Low latency matrix multiply unit [patent_app_type] => utility [patent_app_number] => 18/444249 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6250 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444249
Low latency matrix multiply unit Feb 15, 2024 Issued
Array ( [id] => 19320149 [patent_doc_number] => 20240241693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/426504 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426504
MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH OPERATIONS Jan 29, 2024 Abandoned
Array ( [id] => 19313474 [patent_doc_number] => 12039290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-16 [patent_title] => Multiply accumulate (MAC) unit with split accumulator [patent_app_type] => utility [patent_app_number] => 18/408296 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408296
Multiply accumulate (MAC) unit with split accumulator Jan 8, 2024 Issued
Array ( [id] => 19129464 [patent_doc_number] => 20240134817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => RECONFIGURABLE ARITHMETIC ENGINE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/401571 [patent_app_country] => US [patent_app_date] => 2023-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401571
Reconfigurable arithmetic engine circuit Dec 30, 2023 Issued
Array ( [id] => 19719421 [patent_doc_number] => 12204961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Resistive and digital processing cores [patent_app_type] => utility [patent_app_number] => 18/528086 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528086
Resistive and digital processing cores Dec 3, 2023 Issued
Array ( [id] => 19327626 [patent_doc_number] => 12045309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-23 [patent_title] => Systems and methods for performing matrix multiplication with a plurality of processing elements [patent_app_type] => utility [patent_app_number] => 18/523615 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 17842 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523615
Systems and methods for performing matrix multiplication with a plurality of processing elements Nov 28, 2023 Issued
Array ( [id] => 20009819 [patent_doc_number] => 20250148041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => DYNAMIC MAXIMAL CLIQUE ENUMERATION DEVICE AND METHOD BASED ON FPGA WITH HBM [patent_app_type] => utility [patent_app_number] => 18/833896 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18833896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/833896
Dynamic maximal clique enumeration device and method based on FPGA with HBM Nov 27, 2023 Issued
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