Search

Matthew D. Sandifer

Examiner (ID: 15602, Phone: (571)270-5175 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2151, 2193
Total Applications
846
Issued Applications
683
Pending Applications
44
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17187451 [patent_doc_number] => 20210334336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => FUNCTION GENERATION DEVICE, FUNCTION GENERATION METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/272439 [patent_app_country] => US [patent_app_date] => 2019-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17272439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/272439
Function generation apparatus, method for generating function, and storage medium Sep 1, 2019 Issued
Array ( [id] => 18046608 [patent_doc_number] => 11520562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => System to perform unary functions using range-specific coefficient sets [patent_app_type] => utility [patent_app_number] => 16/557959 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 15425 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557959
System to perform unary functions using range-specific coefficient sets Aug 29, 2019 Issued
Array ( [id] => 15563043 [patent_doc_number] => 20200065933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SIGNAL PROCESSORS AND METHODS FOR ESTIMATING TRANSFORMATIONS BETWEEN SIGNALS WITH LEAST SQUARES [patent_app_type] => utility [patent_app_number] => 16/557929 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557929
Signal processors and methods for estimating transformations between signals with least squares Aug 29, 2019 Issued
Array ( [id] => 16758455 [patent_doc_number] => 10977003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Linear feedback shift register with near-maximal length sequences [patent_app_type] => utility [patent_app_number] => 16/553510 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553510 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553510
Linear feedback shift register with near-maximal length sequences Aug 27, 2019 Issued
Array ( [id] => 16926993 [patent_doc_number] => 11048476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Non-linear feedback shift register [patent_app_type] => utility [patent_app_number] => 16/553460 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 10478 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553460
Non-linear feedback shift register Aug 27, 2019 Issued
Array ( [id] => 15919353 [patent_doc_number] => 10656914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Methods and instructions for a 32-bit arithmetic support using 16-bit multiply and 32-bit addition [patent_app_type] => utility [patent_app_number] => 16/545132 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545132 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545132
Methods and instructions for a 32-bit arithmetic support using 16-bit multiply and 32-bit addition Aug 19, 2019 Issued
Array ( [id] => 17209410 [patent_doc_number] => 11169782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Arithmetic logic unit, data processing system, method and module [patent_app_type] => utility [patent_app_number] => 16/540547 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4837 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540547
Arithmetic logic unit, data processing system, method and module Aug 13, 2019 Issued
Array ( [id] => 16630329 [patent_doc_number] => 20210048982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => PARTIAL PRODUCT FLOATING-POINT MULTIPLICATION CIRCUITRY OPERAND SUMMATION [patent_app_type] => utility [patent_app_number] => 16/538985 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16538985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/538985
PARTIAL PRODUCT FLOATING-POINT MULTIPLICATION CIRCUITRY OPERAND SUMMATION Aug 12, 2019 Abandoned
Array ( [id] => 17423022 [patent_doc_number] => 11256476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Multiple mode arithmetic circuit [patent_app_type] => utility [patent_app_number] => 16/535878 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16535878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/535878
Multiple mode arithmetic circuit Aug 7, 2019 Issued
Array ( [id] => 16130431 [patent_doc_number] => 10698976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Low latency matrix multiply unit [patent_app_type] => utility [patent_app_number] => 16/529662 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11246 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529662
Low latency matrix multiply unit Jul 31, 2019 Issued
Array ( [id] => 17394729 [patent_doc_number] => 11243743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Optimization of neural networks using hardware calculation efficiency and adjustment factors [patent_app_type] => utility [patent_app_number] => 16/528982 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528982 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528982
Optimization of neural networks using hardware calculation efficiency and adjustment factors Jul 31, 2019 Issued
Array ( [id] => 17252810 [patent_doc_number] => 11188299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Repurposed hexadecimal floating point data path [patent_app_type] => utility [patent_app_number] => 16/527138 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3949 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527138
Repurposed hexadecimal floating point data path Jul 30, 2019 Issued
Array ( [id] => 18356696 [patent_doc_number] => 11645096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Computer architecture for performing multiplication using correlithm objects in a correlithm object processing system [patent_app_type] => utility [patent_app_number] => 16/521416 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 34780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521416
Computer architecture for performing multiplication using correlithm objects in a correlithm object processing system Jul 23, 2019 Issued
Array ( [id] => 16584713 [patent_doc_number] => 20210019115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SYSTEM AND METHOD FOR SUPPORTING ALTERNATE NUMBER FORMAT FOR EFFICIENT MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 16/511085 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511085
System and method for supporting alternate number format for efficient multiplication Jul 14, 2019 Issued
Array ( [id] => 17187449 [patent_doc_number] => 20210334334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => TWIDDLE FACTOR GENERATING CIRCUIT FOR AN NTT PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/259065 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17259065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/259065
TWIDDLE FACTOR GENERATING CIRCUIT FOR AN NTT PROCESSOR Jul 8, 2019 Abandoned
Array ( [id] => 17069237 [patent_doc_number] => 20210271453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => ARITHMETIC LOGIC UNIT, MULTIPLY-ACCUMULATE OPERATION DEVICE, MULTIPLY-ACCUMULATE OPERATION CIRCUIT, AND MULTIPLY-ACCUMULATE OPERATION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/258309 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17258309 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/258309
Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation circuit, and multiply-accumulate operation system Jul 4, 2019 Issued
Array ( [id] => 17263851 [patent_doc_number] => 20210376836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SIGNAL PROCESSING CIRCUIT, SIGNAL PROCESSING DEVICE, AND SIGNAL PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/250310 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250310
Signal processing circuit, signal processing device, and signal processing method using logic circuit Jul 4, 2019 Issued
Array ( [id] => 16543943 [patent_doc_number] => 20200410358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => EFFICIENT ARTIFICIAL INTELLIGENCE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 16/457512 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457512 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457512
EFFICIENT ARTIFICIAL INTELLIGENCE ACCELERATOR Jun 27, 2019 Abandoned
Array ( [id] => 15027435 [patent_doc_number] => 20190324722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => VARIABLE PRECISION FLOATING-POINT MULTIPLIER [patent_app_type] => utility [patent_app_number] => 16/451759 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451759
Variable precision floating-point multiplier Jun 24, 2019 Issued
Array ( [id] => 16529732 [patent_doc_number] => 20200403813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => METHOD AND APPARATUS TO PROVIDE MEMORY BASED PHYSICALLY UNCLONABLE FUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/447887 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447887
Method and apparatus to provide memory based physically unclonable functions Jun 19, 2019 Issued
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