
Matthew D. Sandifer
Examiner (ID: 15602, Phone: (571)270-5175 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183, 2151, 2193 |
| Total Applications | 846 |
| Issued Applications | 683 |
| Pending Applications | 44 |
| Abandoned Applications | 135 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15903437
[patent_doc_number] => 20200151238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => Processor and Methods Configured to Provide a Low-Complexity Input/Output Pruning Fast Fourier Transform
[patent_app_type] => utility
[patent_app_number] => 16/444946
[patent_app_country] => US
[patent_app_date] => 2019-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6422
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444946
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/444946 | Processor and Methods Configured to Provide a Low-Complexity Input/Output Pruning Fast Fourier Transform | Jun 17, 2019 | Abandoned |
Array
(
[id] => 16514994
[patent_doc_number] => 20200394252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => INTEGRATOR VOLTAGE SHIFTING FOR IMPROVED PERFORMANCE IN SOFTMAX OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/439246
[patent_app_country] => US
[patent_app_date] => 2019-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4040
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439246
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/439246 | Integrator voltage shifting for improved performance in softmax operation | Jun 11, 2019 | Issued |
Array
(
[id] => 17091545
[patent_doc_number] => 11119733
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Execution unit configured to evaluate functions using at least one multiplier circuit
[patent_app_type] => utility
[patent_app_number] => 16/427828
[patent_app_country] => US
[patent_app_date] => 2019-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 16715
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427828
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/427828 | Execution unit configured to evaluate functions using at least one multiplier circuit | May 30, 2019 | Issued |
Array
(
[id] => 15638491
[patent_doc_number] => 10592239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-17
[patent_title] => Matrix computation engine
[patent_app_type] => utility
[patent_app_number] => 16/423702
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6320
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423702
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/423702 | Matrix computation engine | May 27, 2019 | Issued |
Array
(
[id] => 16470212
[patent_doc_number] => 20200371749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-26
[patent_title] => MULTIPLIER CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/417866
[patent_app_country] => US
[patent_app_date] => 2019-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14399
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417866
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/417866 | Multiplier circuit | May 20, 2019 | Issued |
Array
(
[id] => 17715564
[patent_doc_number] => 11379556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Apparatus and method for matrix operations
[patent_app_type] => utility
[patent_app_number] => 16/417937
[patent_app_country] => US
[patent_app_date] => 2019-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8195
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417937
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/417937 | Apparatus and method for matrix operations | May 20, 2019 | Issued |
Array
(
[id] => 14782643
[patent_doc_number] => 20190266219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => TECHNOLOGIES FOR PERFORMING MACRO OPERATIONS IN MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/411730
[patent_app_country] => US
[patent_app_date] => 2019-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6492
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411730
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/411730 | Technologies for performing macro operations in memory | May 13, 2019 | Issued |
Array
(
[id] => 15182171
[patent_doc_number] => 20190361677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => RANDOM NUMBER GENERATOR AND METHOD FOR GENERATING RANDOM NUMBERS
[patent_app_type] => utility
[patent_app_number] => 16/410701
[patent_app_country] => US
[patent_app_date] => 2019-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3582
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/410701 | Random number generator and method for generating random numbers | May 12, 2019 | Issued |
Array
(
[id] => 17621812
[patent_doc_number] => 11340868
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => Execution unit for evaluating functions using newton raphson iterations
[patent_app_type] => utility
[patent_app_number] => 16/395502
[patent_app_country] => US
[patent_app_date] => 2019-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 15839
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395502
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/395502 | Execution unit for evaluating functions using newton raphson iterations | Apr 25, 2019 | Issued |
Array
(
[id] => 14688985
[patent_doc_number] => 20190243608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => Error Bounded Multiplication by Invariant Rationals
[patent_app_type] => utility
[patent_app_number] => 16/388177
[patent_app_country] => US
[patent_app_date] => 2019-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8950
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388177
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/388177 | Error bounded multiplication by invariant rationals | Apr 17, 2019 | Issued |
Array
(
[id] => 15167977
[patent_doc_number] => 10489484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-26
[patent_title] => Matrix multiplication on a systolic array
[patent_app_type] => utility
[patent_app_number] => 16/381530
[patent_app_country] => US
[patent_app_date] => 2019-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12031
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381530
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/381530 | Matrix multiplication on a systolic array | Apr 10, 2019 | Issued |
Array
(
[id] => 19045684
[patent_doc_number] => 11934797
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Mechanism to perform single precision floating point extended math operations
[patent_app_type] => utility
[patent_app_number] => 16/375307
[patent_app_country] => US
[patent_app_date] => 2019-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 28
[patent_no_of_words] => 22234
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375307
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/375307 | Mechanism to perform single precision floating point extended math operations | Apr 3, 2019 | Issued |
Array
(
[id] => 17651370
[patent_doc_number] => 11354097
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-07
[patent_title] => Compressor circuit, Wallace tree circuit, multiplier circuit, chip, and device
[patent_app_type] => utility
[patent_app_number] => 16/623385
[patent_app_country] => US
[patent_app_date] => 2019-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 10873
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16623385
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/623385 | Compressor circuit, Wallace tree circuit, multiplier circuit, chip, and device | Apr 3, 2019 | Issued |
Array
(
[id] => 17581069
[patent_doc_number] => 20220137924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => DYNAMIC BIAS ANALOG VECTOR-MATRIX MULTIPLICATION OPERATION CIRCUIT AND OPERATION CONTROL METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 17/434099
[patent_app_country] => US
[patent_app_date] => 2019-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5310
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17434099
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/434099 | Dynamic bias analog vector-matrix multiplication operation circuit and operation control method therefor | Apr 2, 2019 | Issued |
Array
(
[id] => 15952659
[patent_doc_number] => 10664234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-26
[patent_title] => Spatial predicates evaluation on geohash-encoded geographical regions
[patent_app_type] => utility
[patent_app_number] => 16/361850
[patent_app_country] => US
[patent_app_date] => 2019-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 33
[patent_no_of_words] => 22317
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16361850
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/361850 | Spatial predicates evaluation on geohash-encoded geographical regions | Mar 21, 2019 | Issued |
Array
(
[id] => 16826565
[patent_doc_number] => 20210141858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-13
[patent_title] => DATA PREDICTION DEVICE, METHOD, AND PROGRAM
[patent_app_type] => utility
[patent_app_number] => 17/044799
[patent_app_country] => US
[patent_app_date] => 2019-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5071
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17044799
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/044799 | DATA PREDICTION DEVICE, METHOD, AND PROGRAM | Mar 19, 2019 | Abandoned |
Array
(
[id] => 17643865
[patent_doc_number] => 20220171603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => MULTIPLY-ACCUMULATE CALCULATION DEVICE, LOGICAL CALCULATION DEVICE, NEUROMORPHIC DEVICE, AND MULTIPLY-ACCUMULATE CALCULATION METHOD
[patent_app_type] => utility
[patent_app_number] => 17/439992
[patent_app_country] => US
[patent_app_date] => 2019-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9103
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17439992
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/439992 | MULTIPLY-ACCUMULATE CALCULATION DEVICE, LOGICAL CALCULATION DEVICE, NEUROMORPHIC DEVICE, AND MULTIPLY-ACCUMULATE CALCULATION METHOD | Mar 18, 2019 | Abandoned |
Array
(
[id] => 16801985
[patent_doc_number] => 10996929
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => High quality down-sampling for deterministic bit-stream computing
[patent_app_type] => utility
[patent_app_number] => 16/352933
[patent_app_country] => US
[patent_app_date] => 2019-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 9540
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352933
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/352933 | High quality down-sampling for deterministic bit-stream computing | Mar 13, 2019 | Issued |
Array
(
[id] => 16209200
[patent_doc_number] => 20200242190
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => APPARATUS AND METHOD FOR COMBINING ANALOG NEURAL NET WITH FPGA ROUTING IN A MONOLITHIC INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/353409
[patent_app_country] => US
[patent_app_date] => 2019-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6550
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353409
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/353409 | Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit | Mar 13, 2019 | Issued |
Array
(
[id] => 16285410
[patent_doc_number] => 20200279012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-03
[patent_title] => Resistive Memory Device For Matrix-Vector Multiplications
[patent_app_type] => utility
[patent_app_number] => 16/289754
[patent_app_country] => US
[patent_app_date] => 2019-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8471
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289754
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/289754 | Resistive memory device for matrix-vector multiplications | Feb 28, 2019 | Issued |