Search

Matthew D. Sandifer

Examiner (ID: 15602, Phone: (571)270-5175 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183, 2151, 2193
Total Applications
846
Issued Applications
683
Pending Applications
44
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15654401 [patent_doc_number] => 20200089731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => CALCULATION APPARATUS [patent_app_type] => utility [patent_app_number] => 16/289084 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289084
Optimization problem solving calculation apparatus Feb 27, 2019 Issued
Array ( [id] => 14798337 [patent_doc_number] => 10402172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Multi-source entropy and randomness aggregation and distribution network [patent_app_type] => utility [patent_app_number] => 16/288722 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288722
Multi-source entropy and randomness aggregation and distribution network Feb 27, 2019 Issued
Array ( [id] => 14782641 [patent_doc_number] => 20190266218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => MATRIX COMPUTATION WITHIN A RECONFIGURABLE PROCESSOR FABRIC [patent_app_type] => utility [patent_app_number] => 16/286891 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286891
MATRIX COMPUTATION WITHIN A RECONFIGURABLE PROCESSOR FABRIC Feb 26, 2019 Abandoned
Array ( [id] => 14506273 [patent_doc_number] => 20190196791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => RANDOM NUMBER GENERATION METHOD AND DEVICE UTILIZED IN COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 16/287617 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287617
Random number generation method and device utilized in computer system Feb 26, 2019 Issued
Array ( [id] => 16032923 [patent_doc_number] => 10678885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Memory device for matrix-vector multiplications [patent_app_type] => utility [patent_app_number] => 16/284702 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7007 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284702
Memory device for matrix-vector multiplications Feb 24, 2019 Issued
Array ( [id] => 16690480 [patent_doc_number] => 20210072958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => ANALOG ARITHMETIC UNIT [patent_app_type] => utility [patent_app_number] => 16/975013 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16975013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/975013
Analog arithmetic unit Feb 21, 2019 Issued
Array ( [id] => 16818902 [patent_doc_number] => 11003734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Calculating device, calculation program, recording medium, and calculation method [patent_app_type] => utility [patent_app_number] => 16/282688 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 18308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16282688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/282688
Calculating device, calculation program, recording medium, and calculation method Feb 21, 2019 Issued
Array ( [id] => 16927059 [patent_doc_number] => 11048542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Dynamical switching between EPT and shadow page tables for runtime processor verification [patent_app_type] => utility [patent_app_number] => 16/333987 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 20898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16333987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/333987
Dynamical switching between EPT and shadow page tables for runtime processor verification Feb 21, 2019 Issued
Array ( [id] => 16772964 [patent_doc_number] => 10984072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Fast fourier transform (FFT) circuit with an integrated half-bin offset [patent_app_type] => utility [patent_app_number] => 16/280150 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280150
Fast fourier transform (FFT) circuit with an integrated half-bin offset Feb 19, 2019 Issued
Array ( [id] => 16416506 [patent_doc_number] => 10824397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Random number generation [patent_app_type] => utility [patent_app_number] => 16/272343 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2499 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272343 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272343
Random number generation Feb 10, 2019 Issued
Array ( [id] => 16241335 [patent_doc_number] => 20200258569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => MULTI-BIT DOT PRODUCT ENGINE [patent_app_type] => utility [patent_app_number] => 16/271811 [patent_app_country] => US [patent_app_date] => 2019-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/271811
Multi-bit dot product engine Feb 8, 2019 Issued
Array ( [id] => 14379617 [patent_doc_number] => 20190163721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => EFFICIENT STORAGE OF APPROXIMATE ORDER STATISTICS OF REAL NUMBERS [patent_app_type] => utility [patent_app_number] => 16/264581 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/264581
Efficient storage of approximate order statistics of real numbers Jan 30, 2019 Issued
Array ( [id] => 15936357 [patent_doc_number] => 20200159812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => COMPRESSION-ENCODING SCHEDULED INPUTS FOR MATRIX COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 16/261199 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261199
Compression-encoding scheduled inputs for matrix computations Jan 28, 2019 Issued
Array ( [id] => 16200580 [patent_doc_number] => 10725743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => System and method for generating random numbers [patent_app_type] => utility [patent_app_number] => 16/253062 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2606 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253062
System and method for generating random numbers Jan 20, 2019 Issued
Array ( [id] => 18174057 [patent_doc_number] => 11573767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Calculation processor and calculation method for determining an exponential function [patent_app_type] => utility [patent_app_number] => 16/957979 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5020 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16957979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/957979
Calculation processor and calculation method for determining an exponential function Jan 14, 2019 Issued
Array ( [id] => 16160559 [patent_doc_number] => 20200218512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Decentralized Random Number Generator [patent_app_type] => utility [patent_app_number] => 16/242780 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242780 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242780
Decentralized random number generator Jan 7, 2019 Issued
Array ( [id] => 15902811 [patent_doc_number] => 20200150925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS [patent_app_type] => utility [patent_app_number] => 16/242998 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242998 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242998
FPGA logic cell with improved support for counters Jan 7, 2019 Issued
Array ( [id] => 16116247 [patent_doc_number] => 20200210146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => BINARY PARALLEL ADDER AND MULTIPLIER [patent_app_type] => utility [patent_app_number] => 16/237104 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237104
Binary parallel adder and multiplier Dec 30, 2018 Issued
Array ( [id] => 16116987 [patent_doc_number] => 20200210516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR FAST FOURIER TRANSFORM CONFIGURATION AND COMPUTATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/236464 [patent_app_country] => US [patent_app_date] => 2018-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236464 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236464
Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions Dec 28, 2018 Issued
Array ( [id] => 15398969 [patent_doc_number] => 10540141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method and apparatus for use in the design and manufacture of integrated circuits [patent_app_type] => utility [patent_app_number] => 16/229499 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 7771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229499
Method and apparatus for use in the design and manufacture of integrated circuits Dec 20, 2018 Issued
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