
Matthew D. Sandifer
Examiner (ID: 15602, Phone: (571)270-5175 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183, 2151, 2193 |
| Total Applications | 846 |
| Issued Applications | 683 |
| Pending Applications | 44 |
| Abandoned Applications | 135 |
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|---|---|---|---|
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